View F81865_4595052.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

F81865 may, 2010 v0.28p F81865 super io with 6 uarts release date: may, 2010 version: v0.28p
F81865 may, 2010 v0.28p F81865 datasheet revision history version date page revision history v0.20p 2008/10/9 - release version v0.21p 2008/10/23 92 add gpio base address register v0.22p 2008/10/30 130 update application circuit v0.23p 2008/12/17 - 1. pin 82 pwr type update to vbat 2. update uart clock register 3. revise uart name from uart0~5 to uart1~6 4. add ir & part of uart 6 function at pin 9, 10, 11 5. add bypass mode at acpi control register. 6. add electrical characteristics 7. checking typing v0.24p 2008/12/25 made correction & clarification v0.25p 2009/6/17 z made correction & clarification z revise index 96h bit 3-0 z update application circuit v0.26p 2009/9/17 made correction & clarification modify electrical characteristics v0.27p 2009/12/07 made correction & clarification modify application circuit (sheet 4) v0.28p 2010/5/24 made correction & clarification add ovt# smi mode to index 2h bit 5-4 & figure 7.3 enhanced fan description & count (section 7.6.1 fan) modify rs485 enable register for com 1~6 index f0h, bit 4 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support app liances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. customers using or selling these products for use in such applications do so at their own risk and agr ee to fully indemnify fintek for any damages resulting from such improper use or sales.
F81865 may, 2010 v0.28p table of content 1. general descrip tion ......................................................................................................... ............................ 5 2. featur e list ................................................................................................................ .................................. 5 3. key spec ification ........................................................................................................... .............................. 7 4. block diagram............................................................................................................... ............................... 8 5. pin conf iguration ........................................................................................................... .............................. 9 6. pin de scription............................................................................................................. .............................. 10 6.1 powe r pin .................................................................................................................. ............................ 10 6.2 lpc in terface.............................................................................................................. ............................11 6.3 fdc ........................................................................................................................ ................................11 6.4 uart ....................................................................................................................... .............................. 13 6.5 paralle l port .............................................................................................................. ............................. 16 6.6 hardware monitor ........................................................................................................... ....................... 17 6.7 spi, gpio, sir............................................................................................................. ......................... 17 6.8 acpi func tion pins ......................................................................................................... ...................... 18 6.9 kbc fu nction ............................................................................................................... ......................... 19 6.10 rtc function .............................................................................................................. .......................... 19 7. function description ........................................................................................................ .......................... 20 7.1. power on st rapping option ................................................................................................. .................. 20 7.2. fdc ....................................................................................................................... ................................ 20 7.3. uart ...................................................................................................................... ............................... 34 7.4. para llel port ............................................................................................................. .............................. 37 7.5. keyboard controller....................................................................................................... ........................ 41 7.6. hardware monitor .......................................................................................................... ........................ 43 7.7. spi in terface............................................................................................................. ............................. 64 7.8. acpi function ............................................................................................................. .......................... 65 7.9. watchdog ti mer func tion................................................................................................... ................... 65 7.10. rtc function ............................................................................................................. ........................... 66 8. register description ........................................................................................................ .......................... 69 8.1 global contro l registers ................................................................................................... .................... 75 8.2 fdc regist ers (cr00) ....................................................................................................... ................... 83 8.3 parallel port registers (cr03) ............................................................................................. ................. 85 8.4 hardware monito r registers (cr04) .......................................................................................... ........... 86 8.5 kbc regist ers (cr05) ....................................................................................................... ................... 86 8.6 gpio regi sters (c r06)...................................................................................................... ................... 87
F81865 may, 2010 v0.28p 8.7 wdt regist ers (cr07)....................................................................................................... ................. 102 8.8 spi regist ers (cr08) ....................................................................................................... ................... 102 8.9 pme and acpi r egisters (cr0a) .............................................................................................. ......... 105 8.10 rtc regi sters (cr0b) ...................................................................................................... .................. 108 8.11 uart1 registers (cr10) .................................................................................................... ................ 108 8.12 uart2 regi sters (cr11) .................................................................................................... .................110 8.13 uart3 registers (cr12) .................................................................................................... .................112 8.14 uart4 registers (cr13) .................................................................................................... .................113 8.15 uart5 registers (cr14) .................................................................................................... .................115 8.16 uart6 registers (cr15) .................................................................................................... .................117 9. electrical characteristics .................................................................................................. ........................119 10. ordering informat ion....................................................................................................... ......................... 122 11. package di mensions ......................................................................................................... ...................... 123 12. applicatio n circ uit ........................................................................................................ ............................ 124
F81865 may, 2010 v0.28p 5 1. general description the F81865 is the featured io chip for industrial pc system. equipped with one ieee 1284 parallel port, 6 uart ports with 9-bit protocol, kbc, serial peripheral interface (spi), sir and one fdc. the F81865 integrated with hardware monitor, 7 sets of voltage sensor, 2 sets of creative auto-controlling fans and 2 temperature sensor pins for the accurate dual current type temperature measurement for cp u thermal diode or external transistors 2n3906. the F81865 provides flexible features for multi-directional application. for instance, supports 53 gpio pins, irq sharing function designed in uart feature for particular usage and accurate current mode h/w monitor will be worth in measurement of temperature, the F81865 also integrated spi interface. the spi interface is for bios usage including bridge function. others, the F81865 supports newest intel peci interfaces for new generational cpu temperature use. furthermore, F81865 provides independent rtc function. these features as above description will help you more and improve product value. finally, the F81865 is powered by 3.3v voltage, with the lpc interface in the package of 128-pqfp. 2. feature list general functions ? comply with lpc 1.1 ? support acpi 3.0 ? provides one fdc, kbc and parallel port ? provide 6 fully functional uart and 1 sir ? 9-bit protocol for uarts ? support irq sharing function. ? h/w monitor functions ? spi interface for bios ? rtc function ? support peci 1.0 interface ? 53 gpio pins for flexible application ? 24/48 mhz clock input ? packaged in 128-pqfp and powered by 3.3vcc
F81865 may, 2010 v0.28p 6 fdc ? compatible with ibm pc at disk drive systems ? variable write pre-compensation with track selectable capability ? support vertical recording format ? dma enable logic ? 16-byte data fifos ? support floppy disk drives and tape drives ? detects all overrun and under run conditions ? built-in address mark detection circuit to simplify the read electronics ? completely compatible with industry standard 82077 ? 360k/720k/1.2m/1.44m/2.88m format; 250k, 300k, 500k, 1m, 2m bps data transfer rate uart ? provide 6 fully functional uart ? 6 high-speed 16c550 compatible uart with 16-byte fifos ? fully programmable serial-interface characteristics ? baud rate supports 115.2k, max. up to 1.5m ? support irq 3,4,5,6,7,8,9,10,11 sharing ? provide 9-bits function for gaming machine ? support irda version 1.0 sir protocol parallel port ? one ps/2 compatible bi-directional parallel port ? support enhanced parallel port (epp) ? compatible with ieee 1284 specification ? support extended capabilities port (ecp) ? compatible with ieee 1284 ? enhanced printer port back-drive current protection keyboard controller ? compatibility with the 8042 ? support ps/2 mouse ? support both interrupt and polling modes ? hardware gate a20 and hardware keyboard reset hardware monitor functions ? 2 dual current type ( 3 ) thermal inputs for cpu thermal diode and 2n3906 transistors ? temperature range -40 ~1 27 ? 7 sets voltage monitoring (4 external and 3 internal powers) ? high limit signal (pme#) for vcore level
F81865 may, 2010 v0.28p 7 ? 2 fan speed monitoring inputs ? 2 fan speed pwm/dc control outputs(support 3 wire and 4 wire fans) ? issue pme# and ovt# hardware signals output ? case intrusion detection circuit ? watchdog# comparison of all monitored values ? integrate intel peci 1.0 interface serial peripheral interface compatible ? support spi bridge function for bios use rtc function ? rtc for time synchronizing. ? provide 256 bytes ram for cmos setting save. ? 32.768k crystal input ? stand alone vbat power input requirement gpio function ? total 53 pins gpio ? interrupt status support ? all gpio can be programmed. ? all gpio pins default mode are od level input. ? supports high/low level/pulse, open drain/push pull function selection package ? 128-pin pqfp green package noted: patented tw207103 tw207104 tw220442 us6788131 b1 twi235231 tw237183 twi263778 3. key specification supply voltage 3.0v to 3.6v operating supply current 10 ma typ.
F81865 may, 2010 v0.28p 8 4. block diagram cpu chipset (nb+sb) usb ide spi floppy irda parallel com led (gpio) temperature voltage fan super h/w monitor + i/o F81865 acpi ac?97 kbc peci rtc
F81865 may, 2010 v0.28p 9 5. pin configuration
F81865 may, 2010 v0.28p 10 6. pin description 6.1 power pin pin no. pin name type description 31, 119 vcc p power supply voltage input with 3.3v 60 vsb p stand-by power supply voltage input 3.3v 84 vbat p battery voltage input 88 rtc_vbat p battery voltage input for rtc 97 avcc p analog power with 3.3v 89 agnd(d-) p analog gnd 22, 73, 128 gnd p digital gnd i/o 12st,5v - ttl level bi-directional pin and schmitt tri gger, 12 ma sink capability, 5v tolerance. i/ood 12t i/ood 14 i/ood 8 i/od 16t,5v - ttl level bi-directional pin, can select to od or out by register, with 12 ma source-sink capability. - ttl level bi-directional pin, can select to od or out by register, with 14 ma source-sink capability. - ttl level bi-directional pin, can select to od or out by register, with 8 ma source-sink capability. - ttl level bi-directional pin,open-drain output with 16 ma source-sink capability, 5v tolerance. od 16,u10,5v i/od 12st,5v o 8,u47,5v - open-drain output pin with 16 ma sink ca pability, pull-up 10k ohms, 5v tolerance. - ttl level bi-directional pin and schmitt trigger, open-drain output with 12 ma sink capability, 5v tolerance. - open-drain pin with 8 ma source-sink capabilit y, pull-up 47k ohms, 5v tolerance. o 8 o 12 - output pin with 8 ma source-sink capability. - output pin with 12 ma source-sink capability. aout - output pin(analog). od 12,5v od 14 od 24 i/o 24t i/o 8t - open-drain output pin with 12 ma sink capability, 5v tolerance. - open-drain output pin with 14 ma sink capability. - open-drain output pin with 24 ma sink capability. - ttl level bi-directional pin, 24ma sink capability. - ttl level bi-directional pin, 8 ma sink capability. in t,5v in st - ttl level input pin,5v tolerance. - ttl level input pin and schmitt trigger. in st,5v - ttl level input pin and schmitt trigger, 5v tolerance. ain - input pin(analog). p - power.
F81865 may, 2010 v0.28p 11 6.2 lpc interface pin no. pin name type pwr description 23 lreset# in st,5v vcc reset signal. it can connect to pcirst# signal on the host. 24 ldrq# o 12 vcc encoded dma request signal. 25 serirq i/o 24t vcc serial irq input/output. 26 lframe# in st vcc indicates start of a new cycle or termination of a broken cycle. 27-30 lad[0:3] i/o 24t vcc these signal lines communicate address, control, and data information over the lpc bus between a host and a peripheral. 32 pciclk in st vcc 33mhz pci clock input. 33 clkin in st vcc system clock input. according to the input frequency 24/48mhz. 6.3 fdc pin no. pin name type pwr description densel# od 14 drive density select. set to 1 ? high data rate.(500kbps, 1mbps) set to 0 ? low data rate. (250kbps, 300kbps) gpio50 i/ood 14 general purpose io. 9 rts6 _ 2# o 14 vcc uart request to send. an active low signal informs the modem or data set that the controller is ready to send data. moa# od 14 motor a on. when set to 0, this pin enables disk drive 0. this is an open drain output. gpio51 i/ood 14 general purpose io. sin6_2 in t,5v uart serial input. used to receive serial data through the communication link. 10 irrx_2 in t,5v vcc infrared receiver input. drva# od 14 drive select a. when set to 0, this pin enables disk drive a. this is an open drain output. gpio52 i/ood 14 general purpose io. sout6_2 o 14 uart serial output. used to transmit serial data out to the communication link. 11 irtx_2 o 14 vcc infrared transmitter output. wdata# od 14 write data. this logic low open drain writes pre-compensation serial data to the selected fdd. an open drain output. gpio53 i/ood 14 general purpose io. 12 dcd6# in t,5v vcc data carrier detect. an active low signal indicates the modem or data set has detected a data carrier.
F81865 may, 2010 v0.28p 12 dir# od 14 direction of the head step motor. an open drain output. logic 1 = outward motion logic 0 = inward motion gpio54 i/ood 14 general purpose io. 13 ri6# in t,5v vcc ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set. step# od 14 step output pulses. this active low open drain output produces a pulse to move the head to another track. gpio55 i/ood 14 general purpose io. 14 cts6# in t,5v vcc clear to send is the modem control input. hdsel# od 14 head select. this open drain output determines which disk drive head is active. logic 1 = side 0 logic 0 = side 1 gpio56 i/ood 14 general purpose io. 15 dtr6# o 14 vcc uart data terminal ready. an active low signal informs the modem or data set that controller is ready to communicate. wgate# od 14 write enable. an open drain output. gpio57 i/ood 14 general purpose io. 16 dsr6# in t,5v vcc data set ready. an active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the uart. rdata# in ts5v the read data input signal from the fdd. gpio60 i/ood 12 general purpose io. 17 dcd5# in t,5v vcc data carrier detect. an active low signal indicates the modem or data set has detected a data carrier. trk0# in t,5v track 0. this schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. gpio61 i/ood 12 general purpose io. 18 ri5# in t,5v vcc ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set. index# in st,5v this schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. gpio62 i/ood 12 general purpose io. 19 cts5# in t,5v vcc clear to send is the modem control input. wpt# in st,5v write protected. this active low schmitt input from the disk drive indicates that the diskette is write-protected. gpio63 i/ood 12 general purpose io. 20 dtr5# o 12 vcc uart data terminal ready. an active low signal informs the modem or data set that controller is ready to communicate.
F81865 may, 2010 v0.28p 13 dskchg# in t,s5v diskette change. this signal is active low at power on and whenever the diskette is removed. gpio64 i/ood 12 general purpose io. 21 dsr5# in t,5v vcc data set ready. an active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the uart. 6.4 uart pin no. pin name type pwr description 120 dcd1# in t,5v vcc data carrier detect. an active low signal indicates th e modem or data set has detected a data carrier. 121 ri1# in t,5v vcc ring indicator. an active low signal indicates that a rin g signal is being received from the modem or data set. 122 cts1# in t,5v vcc clear to send is the modem control input. dtr1# o 8,u47,5v vcc uart data terminal ready. an active low signal inform s the modem or data set that controller is ready t o communicate. internal 47k ohms pulled high and disabl e after power on strapping. 123 pwm_duty_t rap in t,5v vcc power on strapping pin: 1(default): (internal pull high) power on fan speed default duty is 60%.(pwm) 0: (external pull down) power on fan speed default duty is 100%.(pwm) rts1# o 8,u47,5v vcc uart request to send. an active low signal informs th e modem or data set that the controller is ready to sen d data. internal 47k ohms pulled high and disable afte r power on strapping. 124 i2c_addr_tr ap in t,5v vcc power on strapping pin: 1: (internal pull high, default) power on i2c slave address is 8?h5c. 0: (external pull down) power on i2c slave address is 8?h5a. 125 dsr1# in t,5v vcc data set ready. an active low signal indicates th e modem or data set is ready to establish a communication link and transfer data to the uart. sout1 o 8,u47,5v uart serial output. used to transmit serial data out t o the communication link. internal 47k ohms pulled hig h and disable after power on strapping. 126 config4e_2e in t,5v vcc power on strapping: 1(default)configuration register:4e/4f 0 configuration register:2e/2f 127 sin1 in t,5v vcc uart serial input. used to receive serial data throug h the communication link.
F81865 may, 2010 v0.28p 14 1 dcd2# in t,5v vcc data carrier detect. an active low signal indicates th e modem or data set has detected a data carrier. 2 ri2# in t5v vcc ring indicator. an active low signal indicates that a rin g signal is being received from the modem or data set. 3 cts2# in t5v vcc clear to send is the modem control input. dtr2# o 8,u47,5v vcc uart data terminal ready. an active low signal inform s the modem or data set that controller is ready t o communicate. internal 47k ohms pulled high and disabl e after power on strapping. 4 fwh_trap in t,5v vcc power on strapping pin: 1(default): (internal pull high) fwh is enabled. 0: (external pull down) fwh is disabled. rts2# o 8,u47,5v vcc uart request to send. an active low signal informs th e modem or data set that the controller is ready to sen d data. internal 47k ohms pulled high and disable afte r power on strapping. 5 pwm_dc in t5v vcc power on strapping pin: 1: (internal pull high, default) fan control is pwm mode. 0: (external pull down) fan control is linear mode (dac output). 6 dsr2# in t,5v vcc data set ready. an active low signal indicates th e modem or data set is ready to establish a communication link and transfer data to the uart. sout2 o 8,u47,5v uart serial output. used to transmit serial data out t o the communication link. internal 47k ohms pulled hig h and disable after power on strapping. 7 spi_trap in t,5v vcc power on strapping: 1(default internal pull high) spi is disabled. 0 (external pull down) spi is enabled. 8 sin2 in t,5v vcc uart serial input. used to receive serial data throug h the communication link. dcd3# in t,5v data carrier detect. an active low signal indicates th e modem or data set has detected a data carrier. 36 gpio30 i/ood 8 vcc general purpose io. ri3# in t5v ring indicator. an active low signal indicates that a rin g signal is being received from the modem or data set. 37 gpio31 i/ood 8 vcc general purpose io. cts3# in t,5v clear to send is the modem control input. 38 gpio32 i/ood 8 vcc general purpose io. 39 dtr3# o 8 vcc uart data terminal ready. an active low signal inform s the modem or data set that controller is ready t o
F81865 may, 2010 v0.28p 15 communicate. gpio33 i/ood 8 general purpose io. rts3# o 8 uart request to send. an active low signal informs th e modem or data set that the controller is ready to sen d data. 40 gpio34 i/ood 8 vcc general purpose io. dsr3# in t,5v data set ready. an active low signal indicates th e modem or data set is ready to establish a communication link and transfer data to the uart. 41 gpio35 i/ood 8 vcc general purpose io. sout3 o 8 uart serial output. used to transmit serial data out t o the communication link. 42 gpio36 i/ood 8 vcc general purpose io. sin3 in t,5v uart serial input. used to receive serial data throug h the communication link. 43 gpio37 i/ood 8 vcc general purpose io. dcd4# in t,5v data carrier detect. an active low signal indicates th e modem or data set has detected a data carrier. 44 gpio40 i/ood 8 vcc general purpose io. ri4# in t,5v ring indicator. an active low signal indicates that a rin g signal is being received from the modem or data set. 45 gpio41 i/ood 8 vcc general purpose io. cts4# in t,5v clear to send is the modem control input. 46 gpio42 i/ood 8 vcc general purpose io. dtr4# o 8 uart data terminal ready. an active low signal inform s the modem or data set that controller is ready t o communicate. 47 gpio43 i/ood 8 vcc general purpose io. rts4# o 8,u47,5v uart request to send. an active low signal informs th e modem or data set that the controller is ready to sen d data. internal 47k ohms pulled high and disable afte r power on strapping. 48 gpio44 i/ood 8 vcc general purpose io. dsr4# in t,5v data set ready. an active low signal indicates th e modem or data set is ready to establish a communication link and transfer data to the uart. 49 gpio45 i/ood 8 vcc general purpose io. sout4 o 8 uart serial output. used to transmit serial data out t o the communication link. 50 gpio46 i/ood 8 vcc general purpose io. sin4 in t,5v uart serial input. used to receive serial data throug h the communication link. 51 gpio47 i/ood 8 vcc general purpose io.
F81865 may, 2010 v0.28p 16 6.5 parallel port pin no. pin name type pwr description 102 slct in st,5v vcc an active high input on this pin indicates that the printer is selected. refer to the description of the parallel port for definition of this pin in ecp and epp mode. 103 pe in st,5v vcc an active high input on this pin indicates that the printer has detected the end of the paper. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 104 busy in st,5v vcc an active high input indicates that the printer is not ready to receive data. refer to the description of the parallel port for definition of this pin in ecp and epp mode. 105 ack# in st,5v vcc an active low input on this pin indicates that the printer has received data and is ready to accept more data. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 106 slin# od 12,5v vcc output line for detection of printer selection. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 107 init# od 12,5v vcc output line for the printer initialization. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 108 err# in st,5v vcc an active low input on this pin indicates that the printer has encountered an error condition. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 109 afd# od 12,5v vcc an active low output from this pin causes the printer to auto feed a line after a line is printed. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 110 stb# od 12,5v vcc an active low output is used to latch the parallel data into the printer. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 111 pd0 i/o 12st,5v vcc parallel port data bus bit 0. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 112 pd1 i/o 12st,5v vcc parallel port data bus bit 1. 113 pd2 i/o 12st,5v vcc parallel port data bus bit 2. 114 pd3 i/o 12st,5v vcc parallel port data bus bit 3. 115 pd4 i/o 12st,5v vcc parallel port data bus bit 4. 116 pd5 i/o 12st,5v vcc parallel port data bus bit 5. 117 pd6 i/o 12st,5v vcc parallel port data bus bit 6. 118 pd7 i/o 12st,5v vcc parallel port data bus bit 7.
F81865 may, 2010 v0.28p 17 6.6 hardware monitor pin no. pin name type pwr description 93 vin3 ain avcc voltage input 3. 94 vin2 ain avcc voltage input 2. 95 vin1 ain avcc voltage input 1. 96 vin0 (vcore) ain avcc voltage input for vcore. 98 fanin1 in st,5v vcc fan 1 tachometer input. 99 fanctl1 od 12,5v aout vcc fan 1 control output. this pin provides pwm duty-cycle output or a voltage output. 100 fanin2 in st,5v vcc fan 2 tachometer input. 101 fanctl2 od 12,5v aout vcc fan 2 control output. this pin provides pwm duty-cycle output or a voltage output. 90 d2+ ain avcc thermal diode/transistor temperature sensor input. 91 d1+(cpu) ain avcc cpu thermal diode/transistor temperature sensor input. this pin is for cpu use. 92 vref aout avcc voltage reference output. beep od 24 beep pin. 71 gpio16 i/ood 12t vsb general purpose io. peci i/o 8t peci interface pin. 72 gpio17 i/ood 12t vsb general purpose io. 75 ovt# od 12,5v vsb over temperature signal output. 85 copen# in st,5v vbat case open detection #. this pin is connected to a specially designed low power cmos flip-flop backed by the battery for case open state preservation during power loss. 6.7 spi, gpio, sir pin no. pin name type pwr description gpio00 i/ood 12t general purpose io. 52 spi_clk o 12 vsb serial clock output pin for spi device. gpio01 i/ood 12t general purpose io. 53 spi_cs0# od 12 vsb connect this pin to primary bios chip select pin. gpio02 i/ood 12t general purpose io. 54 spi_miso in t,5v vsb spi master in/slave out pin. gpio03 i/ood 12t general purpose io. 55 spi_mosi o 12 vsb spi master out/slave in pin. gpio04 i/ood 12t general purpose io. 56 fwh_dis o 12 vsb firmware hub disable gpio05 i/ood 12t general purpose io. 57 sout6_1 o 12 vsb uart serial output. used to transmit serial data out to the communication link.
F81865 may, 2010 v0.28p 18 irtx_1 o 12 infrared transmitter output. gpio06 i/ood 12t general purpose io. sin6_1 in t,5v uart serial input. used to receive serial data through the communication link. 58 irrx_1 in t,5v vsb infrared receiver input. gpio07 i/ood 12t general purpose io. 59 rts6_1# o 12 vsb uart request to send. an active low signal informs the modem or data set that the controller is ready to send data. gpio10 i/ood 12t general purpose io. 65 led_vsb od 12 vsb power led for vsb. gpio11 i/ood 12t general purpose io. 66 led_vcc od 12 vsb power led for vcc. gpio12 i/ood 12t general purpose io. scl i/ood 12t smbus clock. 67 sout5 o 12 vsb uart serial output. used to transmit serial data out to the communication link. gpio13 i/ood 12t general purpose io. sda i/ood 12t smbus data. 68 sin5 in t,5v vsb uart serial output. used to transmit serial data out to the communication link. gpio14 i/ood 12t general purpose io. 69 rts5# o 12 vsb uart request to send. an active low signal informs the modem or data set that the controller is ready to send data. 6.8 acpi function pins pin no. pin name type pwr description wdtrst# od 12,5v watch dog timer signal output. 70 gpio15 i/ood 12t vsb general purpose io. alert# od 12 alert a signal when temperature over limit setting. 76 gpio20 i/ood 12t vsb general purpose io. 74 pme# od 12,5v vsb generated pme event. it supports the pci pme# interface. this signal allows the peripheral to request the system to wake up. atxpg_in in st,5v atx power good input. 77 gpio21 i/ood 12t vsb general purpose io. pwsin# in st,5v main power switch button input. 78 gpio22 i/ood 12t vsb general purpose io. pwsout# od 12 panel switch output. this pin is low active and pulse output. it is power on request output#. 79 gpio23 i/ood 12t vsb general purpose io. s3# in st,5v s3# input is main power on-off switch input. 80 gpio24 i/ood 12t vsb general purpose io.
F81865 may, 2010 v0.28p 19 ps_on# od 12-5v power supply on-off control output. connect to atx power supply ps_on# signal. 81 gpio25 i/ood 12t vsb general purpose io. pwrok od 12 pwrok function, it is power good signal of vcc, which is delayed 400ms (default) as vcc arrives at 2.8v. 82 gpio26 i/ood 12t vbat general purpose io. rsmrst# od 12 resume reset# function, it is power good signal of vsb, which is delayed 66ms as vsb arrives at 2.8v. 83 gpio27 i/ood 12t vbat general purpose io. 6.9 kbc function pin no. pin name type pwr description 34 kbrst# od 16,u10,5v vcc keyboard reset. this pin is high after system reset. internal pull high 3.3v with 10k ohms. 35 ga20 od 16,u10,5v vcc gate a20 output. this pin is high after system reset. internal pull high 3.3v with 10k ohms. 63 kdata i/od 16t,5v vsb ps/2 keyboard data. 64 kclk i/od 16t,5v vsb ps/2 keyboard clock. 61 mdata i/od 16t,5v vsb ps/2 mouse data. 62 mclk i/od 16t,5v vsb ps/2 mouse clock. 6.10 rtc function pin no. pin name type pwr description 86 rtc_x1 ain rtc_ vbat rtc 32.768khz crystal input. 87 rtc_x2 aout rtc_ vbat rtc 32.768khz crystal output.
F81865 may, 2010 v0.28p 20 7. function description 7.1. power on strapping option the F81865 provides six pins for power on hardwar e strapping to select required functions. see below table for the detail: pin no. symbol value description 1 fwh as a primary bios 4 fwh_trap 0 spi as a primary bios 1 power on fan speed default duty is 60%. ( default) 123 pwm_duty 0 power on fan speed default duty is 100%. 1 spi function disable(default) 7 spi_trap 0 spi function enable 1 the i2c slave address is 8?h5c (default) 124 i2c_addr 0 the i2c slave address is 8?h5a 1 configuration register i/o port is 4e/4f. (default) 126 config4e_2e 0 configuration register i/o port is 2e/2f. 1 fan control mode: pwm mode. ( default) 5 pwm_dc 0 fan control mode: dac mode. 7.2. fdc the floppy disk controller provides the interf ace between a host processor and one floppy disk drive. it integrates a controller and a digital data separator with write pre-compensation, data rate selection logic, microprocessor interface, and a set of registers. the fdc supports data transfer rates of 250 kbps, 300 kbps, 500 kbps, 1 mbps and 2 mbps. it operates in pc/at mode. the fdc configuration is handled by software and a set of configuration re gisters. status, data, and control registers facilitate the interface bet ween the host microprocessor and the disk drive, providing information about the condition and/or stat e of the fdc. these conf iguration registers can select the data rate, enable interrupts, drives, and dma modes, and indicate errors in the data or operation of the fdc/fdd. the controller manage s data transfers using a set of data transfer and control commands. these commands are handled in three phases: command, execution, and result. not all commands utiliz e all these three phases. the below content is about the fdc device regi ster descriptions. all the registers are for software porting reference. status register a (ps/2 mode) ? base + 0 bit name r/w default description 7 intpend r 0 this bit indicates the state of the interrupt output. 6 drv2_n r - 0: a second drive has been installed. 1: a second drive has not been installed.
F81865 may, 2010 v0.28p 21 5 step r 0 this bit indicates the complement of step# disk interface output. 4 trk0_n r - this bit indicates the state of trk0# disk interface input. 3 hdsel r 0 this bit indicates the complement of hdsel# disk interface output. 0: side 0. 1: side 1. 2 index_n r - this bit indicates the state of index# disk interface input. 1 wpt_n r - this bit indicates the state of wpt# disk interface input. 0: disk is write-protected. 1: disk is not write-protected. 0 dir r 0 this bit indicates the comp lement of dir# disk interface output. status register a (model 30 mode) ? base + 0 bit name r/w default description 7 intpend r 0 this bit indicates the state of the interrupt output. 6 drq r 0 this bit indicates the state of the drq signal. 5 step_ff r 0 this bit indicates the complement of latched step# disk interface output. 4 trk0 r - this bit indicates the complement of trk0# disk interface input. 3 hdsel_n r 1 this bit indicates the state of hdsel# disk interface output. 0: side 0. 1: side 1. 2 index r - this bit indicates the comp lement of index# disk interface input. 1 wpt r - this bit indicates the complement of wpt# disk interface input. 0: disk is write-protected. 1: disk is not write-protected. 0 dir_n r 1 this bit indicates the state of dir# disk interface output. 0: head moves in inward direction. 1: head moves in outward direction. status register b (ps/2 mode) ? base + 1 bit name r/w default description 7-6 reserved r 11 reserved. return 11b when read. 5 dr0 r 0 drive select 0. this bit reflec ts the bit0 of digital output register. 4 wdata r 0 this bit changes state at every rising edge of wdata#. 3 rdata r 0 this bit changes state at every rising edge of rdata#. 2 wgate r 0 this bit indicates the complement of wgate# disk interface output. 1 moten1 r 0 this bit indicates the complement of mob# disk interface output. not support in this design. 0 moten0 r 0 this bit indicates the comp lement of moa# disk interface output. status register b (model 30 mode) ? base + 1 bit name r/w default description 7 drv2_n r - 0: a second drive has been installed. 1: a second drive has not been installed.
F81865 may, 2010 v0.28p 22 6 dsb_n r 1 this bit indicates the state of drvb# disk interface output. not support in this design. 5 dsa_n r 1 this bit indicates the state of drva# disk interface output. 4 wdata_ff r 0 this bit is latched at the rising edge of wdata# and is cleared by a read from the digital input register. 3 rdata_ff r 0 this bit is latched at the rising edge of rdata# and is cleared by a read form the digital input register. 2 wgate_ff r 0 this bit is latched at the falling edge of wgate# and is cleared by a read from the digital input register. 1 dsd_n r 1 this bit indicates the complement of drvd# disk interface output. not support in this design. 0 dsc_n r 1 this bit indicates the complement of drvc# disk interface output. not support in this design. digital output register ? base + 2 bit name r/w default description 7 moten3 r 0 motor enable 3. not support in this design. 6 moten2 r 0 motor enable 2. not support in this design. 5 moten1 r/w 0 motor enable 1. used to control mob#. mob# is not sup port in this design. 4 moten0 r/w 0 motor enable 0. used to control moa#. 3 damen r/w 0 dma enable. this bit has two mode of operation. pc-at and model 30 mode: write 1 will enable dma and irq, write 0 will disable dma and irq. ps/2 mode: this bit is reserved. dma and irq are always enabled in ps/2 mode. 2 reset r 0 write 0 to this bit will reset the controller. i will remain in reset condition until a 1 is written. 1 dsd_n r 1 this bit indicates the complement of drvd# disk interface output. not support in this design. 0 dsc_n r 1 this bit indicates the complement of drvc# disk interface output. not support in this design. tape drive register ? base + 3 bit name r/w default description 7-6 reserved r 00 reserved. return 00b when read. 5-4 typeid r 11 reserved in normal function, return 11b when read. if 3 mode fdd function is enabled. these bits indicate the drive type id. 3-2 reserved r 11 reserved. return 11b when read in normal function. return 00b when read in 3 mode fdd function. 1-0 tapesel r/w 0 these bits assign a logical drive number to be a tape drive. main status register ? base + 4 bit name r/w default description 7 rqm r 0 request for master indicates that the cont roller is ready to send or receive data from the up through the fifo.
F81865 may, 2010 v0.28p 23 6 dio r 0 data i/o (direction): 0: the controller is expecting a byte to be written to the data register. 1: the controller is expecting a byte to be read from the data register. 5 non_dma r 0 non dma mode: 0: the controller is in dam mode. 1: the controller is interrupt or software polling mode. 4 fdc_busy r 0 this bit indicate that a read or write command is in process. 3 drv3_busy r 0 fdd number 3 is in seek or calibration condition. fdd number 3 is not support in this design. 2 drv2_busy r 0 fdd number 2 is in seek or calibration condition. fdd number 2 is not support in this design. 1 drv1_busy r 0 fdd number 1 is in seek or calibration condition. fdd number 1 is not support in this design. 0 drv0_busy r 0 fdd number 0 is in seek or calibration condition. data rate select register ? base + 4 bit name r/w default description 7 softrst w 0 a 1 written to this bit will softwa re reset the controller. auto clear after reset. 6 pwrdown w 0 a 1 to this bit will put the controller into low power mode which will turn off the oscillator and data separator circuits. 5 reserved - - return 0 when read. 4-2 precomp w 000 select the value of wr ite precompensation: 250k-1mbps 2mbps 000: default delays default delays 001: 41.67ns 20.8ns 010: 83.34ns 41.17ns 011: 125.00ns 62.5ns 100: 166.67ns 83.3ns 101: 208.33ns 104.2ns 110: 250.00ns 125.00ns 111: 0.00ns (disabled) 0.00ns (disabled) the default value of corresponding data rate: 250kbps: 125ns 300kbps: 125ns 500kbps: 125ns 1mbps: 41.67ns 2mbps: 20.8ns 1-0 drate w 10 data rate select: mfm fm 00: 500kbps 250kbps 01: 300kbps 150kbps 10: 250kbps 125kbps 11: 1mbps illegal data (fifo) register ? base + 5 bit name r/w default description 7-0 data r/w 00h the fifo is used to transfer all commands, data and status between controller and the system. the data register consists of four status registers in a stack with only one register presented to the data bus at a time. the fifo is default disabled and could be enabled via the configure command.
F81865 may, 2010 v0.28p 24 status registers 0 bit name r/w default description 7-6 ic r - interrupt code : 00: normal termination of command. 01: abnormal termination of command. 10: invalid command. 11: abnormal termination caused by poling. 5 se r - seek end. set when a seek or recalibrate or a read or write with implied seek command is completed. 4 ec r - equipment check. 0: no error 1: when a fault signal is received form the fdd or the trk0# signal fails to occur after 77 step pulses. 3 nr r - not ready. 0: drive is ready 1: drive is not ready. 2 hd r - head address. the current head address. 1-0 ds r - drive select. 00: drive a selected. 01: drive b selected. 10: drive c selected. 11: drive d selected. status registers 1 bit name r/w default description 7 en r - end of track. set when the fdc tries to access a sector beyond the final sector of a cylinder. 6 de r - data error. the fdc detect a crc error in either the id field or the data field of a sector. 4 or r - overrun/underrun. set when the fdc is not serviced by the host system within a certain time interval during data transfer. 3 reserved - - unused. this bit is always ?0? 2 nd r - no data. set when the following conditions occurred: 1. the specified sector is not found during any read command. 2. the id field cannot be read without errors during a read id command. 3. the proper sector sequence cann ot be found during a read track command. 1 nw r - no writable set when wpt# is active during execution of write commands.
F81865 may, 2010 v0.28p 25 0 ma r - missing address mark. set when the following conditions occurred: 1. cannot detect an id address mark at the specified track after encountering the index pulse form the index# pin twice. 2. cannot detect a data address mark or a deleted data address mark on the specified track. status registers 2 bit name r/w default description 7 reserved - - unused. this bit is always ?0?. 6 cm r - control mark. set when following conditions occurred: 1. encounters a deleted data address mark during a read data command. 2. encounters a data address mark during a read deleted data command. 5 dd r - data error in data field. the fdc detects a crc error in the data field. 4 wc r - wrong cylinder. set when the track address from the sector id field is different from the track address maintained inside the fdc. 3 se r - scan equal. set if the equal condition is satisfied during execution of the scan command. 2 sn r - scan not satisfied. set when the fdc cannot find a sector on the track which meets the desired condition during any scan command. 1 bc r - bad cylinder. the track address from the sector id fi eld is different from the track address maintained inside the fdc and is equal to ffh which indicates a bad track. 0 md r - missing data address mark. set when the fdc cannot detect a data address mark or a deleted data address mark. status registers 3 bit name r/w default description 7 reserved - - unused. this bit is always ?0?. 6 wp r - write protect. indicates the status of wpt# pin. 5 reserved r - unused. this bit is always ?1?. 4 t0 r - track 0. indicates the status of the trk0# pin. 3 reserved. r - unused. this bit is always ?1?. 2 hd r - head address. indicates the status of the hdsel# pin. 1 ds1 r - 0 ds0 r - drive select. these two bits indicate the ds1, ds0 bits in the command phase.
F81865 may, 2010 v0.28p 26 digital input register (pc-at mode) ? base + 7 bit name r/w default description 7 dskchg r - this bit indicates the complement of dskchg# disk interface input. 6-0 reserved r - reserved. digital input register (ps/2 mode) ? base + 7 bit name r/w default description 7 dskchg r - this bit indicates the complement of dskchg# disk interface input. 6-3 reserved - - reserved. 2-1 drate r 10 these bits indicate the status of the drate programmed through the data rate select register or co nfiguration control register. 0 highden_n r 1 0: 1mbps or 500kbps data rate is chosen. 1: 300kbps or 250kbps data rate is chosen. digital input register (model 30 mode) ? base + 7 bit name r/w default description 7 dskchg_n r - this bit indicates the state of dskchg# disk interface input. 6-4 reserved - - reserved. 3 dmaen r 0 this bit reflects the dma bit in digital output register. 2 nopre r 0 this bit reflects the nopre bit in configuration control register. 1-0 drate r 10 these bits indicate the status of dra te programmed through the data rate select register or config uration control register. configuration control register (pc-at and ps/2 mode) ? base + 7 bit name r/w default description 7-2 reserved - - reserved. 1-0 drate w 10 these bit determine the data rate of the floppy controller. see drate bits in data rate select register. configuration control register (model 30 mode) ? base + 7 bit name r/w default description 7-3 reserved - - reserved. 2 nopre w 0 this bit could be programmed through co nfiguration control register and be read through the bit 2 in digital input r egister in model 30 mode. but it has no functionality. 1-0 drate w 10 these bits determine the data rate of the floppy controller. see drate bits in data rate select register.
F81865 may, 2010 v0.28p 27 fdc commands terminology: c cylinder number 0 -256 d data pattern dir step direction 0: step out 1: step in ds0 drive select 0 ds1 drive select 1 dtl data length ec enable count eot end of track efifo enable fifo 0: fifo is enabled. 1: fifo is disabled. eis enable implied seek fifothr fifo threshold gap alters gap length gpl gap length h/hds head address hlt head load time hut head unload time lock lock efifo, fifothr, ptrtrk bits. prevent these bits from being affected by software reset. mfm mfm or fm mode 0: fm 1: mfm mt multi-track n sector size code. all values up to 07h are allowable. 00: 128 bytes 01: 256 bytes .. .. 07 16 kbytes ncn new cylinder number nd non-dma mode ow overwritten pcn present cylinder number poll polling disable 0: polling is enabled. 1: polling is disabled. pretrk precompensation start track number r sector address rcn relative cylinder number sc sector per cylinder sk skip deleted data address mark srt step rate time st0 status register 0 st1 status register 1 st2 status register 2 st3 status register 3 wgate write gate alters timing of we.
F81865 may, 2010 v0.28p 28 read data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w mt mfm sk 0 0 1 1 0 command code w 0 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w ---------------------------- dtl -------------------------- sector id information prior to command execution execution data transfer between the fdd and system result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. read deleted data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w mt mfm sk 0 1 1 0 0 command code w 0 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w ---------------------------- dtl -------------------------- sector id information prior to command execution execution data transfer between the fdd and system result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution.
F81865 may, 2010 v0.28p 29 r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. read a track phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 mfm 0 0 0 0 1 0 command code w 0 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w ---------------------------- dtl -------------------------- sector id information prior to command execution execution data transfer between the fdd and system. fdd reads contents of all cylinders from index hole to eot. result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. read id phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 mfm 0 0 1 0 1 0 command code w 0 0 0 0 0 hds ds1 ds0 execution the first correct id information on the cylinder is stored in data register. result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution.
F81865 may, 2010 v0.28p 30 r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- disk status after the command has been completed. verify phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w mt mfm sk 1 0 1 1 0 command code w ec 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w -------------------------- dtl/sc ------------------------ sector id information prior to command execution execution no data transfer result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. version phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 1 0 0 0 0 command code result r 1 0 0 1 0 0 0 0 enhanced controller write data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w mt mfm 0 0 0 1 0 1 command code w 0 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- sector id information prior to command
F81865 may, 2010 v0.28p 31 w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w ---------------------------- dtl -------------------------- execution execution data transfer between the fdd and system. result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. write deleted data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w mt mfm 0 0 1 0 0 1 command code w 0 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w ---------------------------- dtl -------------------------- sector id information prior to command execution execution data transfer between the fdd and system. result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution.
F81865 may, 2010 v0.28p 32 format a track phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 mfm 0 0 1 1 0 1 command code w 0 0 0 0 0 hds ds1 ds0 w ------------------------------ n --------------------------- bytes/sector w ---------------------------- sc -------------------------- sectors/cylinder w ---------------------------- gpl -------------------------- gap 3 length w ----------------------------- d --------------------------- data pattern ------------------------------ c --------------------------- w ------------------------------ h --------------------------- w ------------------------------ r --------------------------- execution for each sector ( repeat ) w ----------------------------- n -------------------------- input sector parameter. result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ------------------------- undefined ---------------------- r ------------------------- undefined ---------------------- r -------------------------- undefined ----------------------- r ------------------------- undefined ---------------------- recalibrate phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 0 1 1 1 command code w 0 0 0 0 0 0 ds1 ds0 execution head retracted to track 0 sense interrupt status phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 1 0 0 0 command code result r ---------------------------- st0 -------------------------- r ---------------------------- pcn -------------------------- specify phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 0 0 1 1 command code w |------------------ srt -------------------| |------------------ hut -------------------| w |------------------------------------- srt ---------------------------------------| nd
F81865 may, 2010 v0.28p 33 seek phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 1 1 1 1 command code w 0 0 0 0 0 hds ds1 ds0 w ---------------------------- ncn -------------------------- execution head positioned over proper cylinder on diskette configure phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 1 0 0 1 1 command code w 0 0 0 0 0 hds ds1 ds0 w 0 eis efifo poll |---------------- fifothr ---------------| w ---------------------------- pretrk -------------------------- execution internal registers written relative seek phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 1 dir 0 0 1 1 1 1 command code w 0 0 0 0 0 hds ds1 ds0 w ---------------------------- rcn -------------------------- perpendicular mode phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 1 0 0 1 0 command code w ow 0 d3 d2 d1 d0 gap wgate lock phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w lock 0 0 1 0 1 0 0 command code result r 0 0 0 lock 0 0 0 0 dumpreg phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 1 1 1 0 command code result r -------------------------- pcn ( drive 0 ) ------------------------ r -------------------------- pcn ( drive 0 ) ------------------------
F81865 may, 2010 v0.28p 34 r -------------------------- pcn ( drive 0 ) ------------------------ r -------------------------- pcn ( drive 0 ) ------------------------ r |------------------ srt -------------------| |------------------ hut -------------------| r |------------------------------------- srt ---------------------------------------| nd r -------------------------- sc/eot ------------------------ r lock 0 d3 d2 d1 d0 gap wgate r 0 eis efifo poll |---------------- fifothr ---------------| r ---------------------------- pretrk -------------------------- sense drive status phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 0 1 0 0 command code w 0 0 0 0 0 hds ds1 ds0 result r ---------------------------- st3 -------------------------- status information abut disk drive invalid phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w ---------------------------- in valid codes -------------------------- fdc goes to standby state. result r ---------------------------- st0-------------------------- st0 = 80h 7.3. uart the F81865 provides up to 6 uart ports and supports irq sharing for system application. the uarts are used to convert data between parallel format and serial format. they convert parallel data into serial format on transmission and serial format into parallel data on receiver side. the serial format is formed by one start bit, followed by five to eight data bits, a parity bit if programmed and one ( 1.5 or 2 ) stop bits. the uarts include complete modem control capability and an interrupt system that may be software trailed to the computing time required to handle the communication link. they have fifo mode to reduce the number of interr upts presented to the host. both receiver and transmitter have a 16-byte fifo. the below content is about the uarts device register descripti ons. all the registers are for software porting reference. receiver buffer register ? base + 0 bit name r/w default description 7-0 rbr r 00h the data received. read only when lcr[7] is 0
F81865 may, 2010 v0.28p 35 transmitter holding register ? base + 0 bit name r/w default description 7-0 thr w 00h data to be transmitted. write only when lcr[7] is 0 divisor latch (lsb) ? base + 0 bit name r/w default description 7-0 dll r/w 01h baud generator divisor low byte. access only when lcr[7] is 1. divisor latch (msb) ? base + 1 bit name r/w default description 7-0 dlm r/w 00h baud generator divisor high byte. access only when lcr[7] is 1. interrupt enable register (ier) ? base + 1 bit name r/w default description 7-5 reserved - - reserved. 4 sm2 r/wc 0 this bit is used only in 9-bit mode and always returns ?0? when 9-bit mode is disabled. 0: the receiver could receive data byte. 1: the receiver could only receive address byte and issue an interrupt when the address is received. 3 edssi r/w 0 enable modem status interrupt. access only when lcr[7] is 0. 2 elsi r/w 0 enable line status error in terrupt. access only when lcr[7] is 0. 1 etbfi r/w 0 enable transmitter holding register empty interrupt. access only when lcr[7] is 0. 0 erbfi r/w 0 enable received data available interrupt. access only when lcr[7] is 0. interrupt identification register (iir) ? base + 2 bit name r/w default description 7 fifo_en r 0 0: fifo is disabled 1: fifo is enabled. 6 fifo_en r 0 0: fifo is disabled 1: fifo is enabled. 5-4 reserved - - reserved. 3-1 irq_id r 00 000: interrupt is caused by modem status 001: interrupt is caused by transmitter holding register empty 010: interrupt is caused by received data available. 110: interrupt is caused by character timeout 011: interrupt is caused by line status. 0 irq_pendn r 1 1: interrupt is not pending. 0: interrupt is pending.
F81865 may, 2010 v0.28p 36 fifo control register ? base + 2 bit name r/w default description 7-6 rcv_trig w 00 00: receiver fifo trigger level is 1. 01: receiver fifo trigger level is 4. 10: receiver fifo trigger level is 8. 11: receiver fifo trigger level is 14. 5-3 reserved - - reserved. 2 clrtx r 0 reset the transmitter fifo. 1 clrrx r 0 reset the receiver fifo. 0 fifo_en r 0 0: disable fifo. 1: enable fifo. line control register (lcr) ? base + 3 bit name r/w default description 7 dlab r/w 0 0: divisor latch can?t be accessed. 1: divisor latch can be accessed via base and base+1. 6 setbrk r/w 0 0: transmitter is in normal condition. 1: transmit a break condition. 5 stkpar r/w 0 4 eps r/w 0 3 pen r/w 0 xx0: parity bit is disable 001: parity bit is odd. 011: parity bit is even 101: parity bit is logic 1 111: parity bit is logic 0 2 stb r/w 0 0: stop bit is one bit 1: when word length is 5 bit stop bit is 1.5 bit else stop bit is 2 bit 1-0 wls r/w 00 00: word length is 5 bit 01: word length is 6 bit 10: word length is 7 bit 11: word length is 8 bit modem control register (mcr) ? base + 4 bit name r/w default description 7-5 reserved - - reserved. 4 loop r/w 0 0: uart in normal condition. 1: uart is internal loop back 3 out2 r/w 0 0: all interrupt is disabled. 1: interrupt is enabled (disabled) by ier. 2 out1 r/w 0 read from msr[6] while in loop back mode 1 rts r/w 0 0: rts# is forced to logic 1 1: rts# is forced to logic 0 0 dtr r/w 0 0: dtr# is forced to logic 1 1: dtr# is forced to logic 0 line status register (lsr) ? base + 5 bit name r/w default description 7 rcr_err r 0 0: no error in the fifo when fifo is enabled 1: error in the fifo when fifo is enabled.
F81865 may, 2010 v0.28p 37 6 temt r 1 0: transmitter is in transmitting. 1: transmitter is empty. 5 thre r 1 0: transmitter holding register is not empty. 1: transmitter holding register is empty. 4 bi r 0 0: no break condition detected. 1: a break condition is detected. 3 fe r 0 0: data received has no frame error. 1: data received has frame error. 2 pe r 0 0: data received has no parity error. 1: data received has parity error. 1 oe r 0 0: no overrun condition occurred. 1: an overrun condition occurred. 0 dr r 0 0: no data is ready for read. 1: data is received. modem status register (msr) ? base + 6 bit name r/w default description 7 dcd r - complement of dcd# input. in loop back mo de, this bit is equivalent to out2 in mcr. 6 ri r - complement of ri# input. in loop back mode , this bit is equivalent to out1 in mcr 5 dsr r - complement of dsr# input. in loop back mode , this bit is equivalent to dtr in mcr 4 cts r - complement of cts# input. in loop back mode , this bit is equivalent to rts in mcr 3 ddcd r 0 0: no state changed at dcd#. 1: state changed at dcd#. 2 teri r 0 0: no trailing edge at ri#. 1: a low to high transition at ri#. 1 ddsr r 1 0: no state changed at dsr#. 1: state changed at dsr#. 0 dcts r 1 0: no state changed at cts#. 1: state changed at cts#. scratch register ? base + 7 bit name r/w default description 7-0 scr r/w 00h scratch register. 7.4. parallel port the parallel port in F81865 supports an ibm xt/at compatible parallel port ( spp ), bi-directional parallel port ( bpp ), enhanced parallel port ( epp ), extended capabilities parallel port ( ecp ) mode. refer to the configuration register s for more information on selecting the mode of operation. the below content is about the parallel port device register descriptions. all the registers are for software porting reference.
F81865 may, 2010 v0.28p 38 parallel port data register ? base + 0 bit name r/w default description 7-0 data r/w 00h the output data to dr ive the parallel port data lines. ecp address fifo register ? base + 0 bit name r/w default description 7-0 ecp_afifo r/w 00h access only in ecp parallel port mode and the ecp_mode programmed in the extended control register is 011. the data written to this register is placed in the fifo and tagged as an address/rle. it is auto transmitted by the hardware. the operation is only defined for forward direction. it divide into two parts : bit 7 : 0: bits 6-0 are run length, indicating how many times the next byte to appear (0 = 1time, 1 = 2times, 2 = 3times and so on). 1: bits 6-0 are ecp address. bit 6-0 : address or rle depends on bit 7. device status register ? base + 1 bit name r/w default description 7 busy_n r - inverted version of parallel port signal busy. 6 ack_n r - version of parallel port signal ack#. 5 perror r - version of parallel port signal pe. 4 select r - version of parallel port signal slct. 3 err_n r - version of parallel port signal err#. 2-1 reserved r 11 reserved. return 11b when read. 0 tmout r - this bit is valid only in epp mode. return 1 when in other modes. it indicates that a 10us time out has occurred on the epp bus. 0: no time out error. 1: time out error occurred, write 1 to clear. device control register ? base + 2 bit name r/w default description 7-6 reserved - 11 reserved. return 11b when read. 5 dir r/w 0 0: the parallel port is in output mode. 1: the parallel port is in input mode. it is auto reset to 1 when in spp mode. 4 ackirq_en r/w 0 enable an interr upt at the rising edge of ack#. 3 slin r/w 0 inverted and then drives the parallel port signal slin#. when read, the status of inverted slin# is return. 2 init_n r/w 0 drives the parallel port signal init#. when read, the status of init# is return. 1 afd r/w 0 inverted and then drives the parallel port signal afd#. when read, the status of inverted afd# is return.
F81865 may, 2010 v0.28p 39 0 stb r/w 0 inverted and then drives the parallel port signal stb#. when read, the status of inverted stb# is return. epp address register ? base + 3 bit name r/w default description 7-0 epp_addr r/w 00h write this register will cause the hardwar e to auto transmit the written data to the device with the epp address write protocol. read this register will cause the hardwar e to auto receive data from the device by with the epp address read protocol. epp data register ? base + 4 ? base + 7 bit name r/w default description 7-0 epp_data r/w 00h write this register will cause the hardwar e to auto transmit the written data to the device with the epp data write protocol. read this register will cause the hardwar e to auto receive data from the device by with the epp data read protocol. parallel port data fifo ? base + 400h bit name r/w default description 7-0 c_fifo r/w 00h data written to this fifo is auto trans mitted by the hardware to the device by using standard parallel port protocol. it is only valid in ecp and the ecp_mode is 010b.the operation is only for forward direction. ecp data fifo ? base + 400h bit name r/w default description 7-0 ecp_dfifo r/w 00h data written to this fifo when dir is 0 is auto transmitted by the hardware to the device by using ecp parallel port protocol. data is auto read from device into the fifo when dir is 1 by the hardware by using ecp parallel port protocol. read the fifo will return the content to the system. it is only valid in ecp and the ecp_mode is 011b. ecp test fifo ? base + 400h bit name r/w default description 7-0 t_fifo r/w 00h data may be read, written from system to the fifo in any direction. but no hardware handshake occurred on the parallel port lines. it could be used to test the empty, full and threshold of the fifo. it is only valid in ecp and the ecp_mode is 110b. ecp configuration register a ? base + 400h bit name r/w default description 7 irq_mode r 0 0: interrupt is isa pulse. 1: interrupt is isa level. only valid in ecp and ecp_mode is 111b.
F81865 may, 2010 v0.28p 40 6-4 impid r 001 000: the design is 16-bit implementation. 001: the design is 8-bit implementation (default). 010: the design is 32-bit implementation. 011-111: reserved. only valid in ecp and ecp_mode is 111b. 3 reserved - - reserved. 2 bytetran_n r 1 0: when transmitting there is 1 byte wait ing in the transceiver that does not affect the fifo full condition. 1: when transmitting the state of the full bit includes the byte being transmitted. only valid in ecp and ecp_mode is 111b. 1-0 reserved r 00 return 00 when read. only valid in ecp and ecp_mode is 111b. ecp configuration register b ? base + 401h bit name r/w default description 7 comp r 0 0: only send uncompressed data. 1: compress data before sending. only valid in ecp and ecp_mode is 111b. 6 reserved r 1 reserved. return 1 when read. only valid in ecp and ecp_mode is 111b. 5-3 ecp_irq_ch r 001 000: the interrupt selected with jumper. 001: select irq 7 (default). 010: select irq 9. 011: select irq 10. 100: select irq 11 101: select irq 14. 110: select irq 15. 111: select irq 5. only valid in ecp and ecp_mode is 111b. 2-0 ecp_dma_ch r 011 return the dma channel of ecp parallel port. only valid in ecp and ecp_mode is 111b. extended control register ? base + 402h bit name r/w default description 7-5 ecp_mode r/w 000 000: spp mode. 001: ps/2 parallel port mode. 010: parallel port data fifo mode. 011: ecp parallel port mode. 100: epp mode. 101: reserved. 110: test mode. 111: configuration mode. only valid in ecp. 4 errintr_en r/w 0 0: disable the interrupt generated on the falling edge of err#. 1: enable the interrupt generated on the falling edge of err#. 3 damen r/w 0 0: disable dma. 1: enable dma. dma starts when serviceintr is 0.
F81865 may, 2010 v0.28p 41 2 serviceintr r/w 1 0: enable the following case of interrupt. dmaen = 1: dma mode. dmaen = 0, dir = 0: set to 1 whenever there are writeintrthreshold or more bytes are free in the fifo. dmaen = 0, dir = 0: set to 1 whenever there are readintrthreshold or more bytes are valid to be read in the fifo. 1 fifofull r 0 0: the fifo has at least 1 free byte. 1: the fifo is completely full. 0 fifoempty r 0 0: the fifo contains at least 1 byte. 1: the fifo is completely empty. 7.5. keyboard controller the kbc circuit provides the functions inclu ded a keyboard and/or a ps/2 mouse, and can be used with ibm-compatible personal computers or ps /2-based systems. the controller receives serial data from the keyboard or ps/2 mouse, checks t he parity of the data, and presents the data to the system as a byte of data in its output buffer. the c ontroller will assert an interrupt to the system when data are placed in its output buffer. output buffer the output buffer is an 8-bit read-only register at i/o address 60h. the keyboard controller uses the output buffer to send the scan code receiv ed from the keyboard and data bytes required by commands to the system. input buffer the input buffer is an 8-bit write-only register at i/o address 60h or 64h. writing to address 60h sets a flag to indicate a data write; writing to address 64h sets a flag to indicate a command write. data written to i/o address 60h is sent to keyboard through the controller's input buffer only if the input buffer full bit in the status register is ?0?. status register the status register is an 8-bit read-only register at i/o address 64h that holds information about the status of the keyboard controller and interface. it may be read at any time. bit bit function description 0 output buffer full 0: output buffer empty 1: output buffer full 1 input buffer full 0: input buffer empty 1: input buffer full 2 system flag this bit may be set to 0 or 1 by wr iting to the system flag bit in the command byte of the keyboard controller (kccb). it defaults to 0 after a power-on reset.
F81865 may, 2010 v0.28p 42 3 command/data 0: data byte 1: command byte 4 inhibit switch 0: keyboard is inhibited 1: keyboard is not inhibited 5 mouse output buffer 0: muse output buffer empty 1: mouse output buffer full 6 general purpose time-out 0: no time-out error 1: time-out error 7 parity error 0: odd parity 1: even parity (error) commands command function 20h read command byte 60h write command byte bit description 0 enable keyboard interrupt 1 enable mouse interrupt 2 system flag 3 reserve 4 disable keyboard interface 5 disable mouse interface 6 ibm keyboard translate mode 7 reserve a7h disable auxiliary device interface a8h enable auxiliary device interface a9h auxiliary interface test 8?h00: indicate auxiliary interface is ok. 8?h01: indicate auxiliary clock is low. 8?h02: indicate auxiliary clock is high 8?h03: indicate auxiliary data is low 8?h04: indicate auxiliary data is high aah self-test return 55h if self test succeeds abh keyboard interface test 8?h00: indicate keyboard interface is ok. 8?h01: indicate keyboard clock is low. 8?h02: indicate keyboard clock is high 8?h03: indicate keyboard data is low 8?h04: indicate keyboard data is high adh disable keyboard interface
F81865 may, 2010 v0.28p 43 aeh enable keyboard interface c0h read input port(p1) and send data to the system c1h continuously puts the lower four bits of port1 into status register c2h continuously puts the upper four bits of port1 into status register cah read the data written by cbh command. cbh written a scratch data. this by te could be read by cah command. d0h send port2 value to the system d1h only set/reset gatea20 line based on the system data bit 1 d2h send data back to the system as if it came from keyboard d3h send data back to the system as if it came from muse d4h output next received byte of data from system to mouse feh low pulse on kbrst# about 6 s kbc command description ps/2 wakeup function the kbc supports keyboard and mouse wakeup function. kbc will assert pme or psout# signal. those wakeup conditions are co ntrolled by configuration register. 7.6. hardware monitor 7.6.1 general description voltage for the 8-bit adc has the 8mv lsb, the maximu m input voltage of the analog pin is 2.04v. therefore the voltage under 2.04v (ex:1.5v) can be di rectly connected to these analog inputs. the voltage higher than 2.04v should be reduced by a factor with external resistors so as to obtain the input range. only 3vcc is an except ion for it is main power of the F81865. therefore 3vcc can directly connect to this chip?s power pin and need no external resistors. there are tw o functions in this pin with 3.3v. the first function is to supply internal analog power of the F81865 and the second function is that voltage with 3.3v is connected to internal serial resistors to monitor the +3.3v voltage. the internal serial resistors are two 150k ohm, so that the internal reduced voltage is half of +3.3v (see figure 7-1). there are four voltage inputs in the F81865 and the voltage divided formula is shown as follows: 2 1 2 v 12 r r r v vin + = + where v +12v is the analog input voltage, for example. if we choose r1=27k, r2=5.1k, the exact i nput voltage for v+12v will be 1.907v, which is within the tolerance. as for application circuit, it can be refer to the figure shown as follows.
F81865 may, 2010 v0.28p 44 vin (< 2.04v) 8-bit adc with 8 mv lsb typical thermister connection r thm voltage inputs 10k, 25 c r vref 10k, 1% r 1 r2 (directly connect to the chip) 3vcc (directly connect to the chip) vin3.3 150k 150k 2n3906 typical bjt connection d+ d- vin (> 2.04v) fig 7-1 pme# interrupt for voltage is shown as figure 7-2. voltage exceeding or going below high limit will cause an interrupt if the prev ious interrupt has been reset by writing ?1? al l the interrupt status register. * voltage pme# mode * *interrupt reset when interrupt status registers are written 1 (p ulse mode ) fig 7-2 temperature sensor the F81865 monitors two remote temperature sensor s. these sensors can be measured from -40c to 127c (for thermal diode) & 0c to 127c (for thermistor). more detail please refer to the register description. remote-sensor transistor manufacturers manufacturer model number panasonic 2sb0709 2n3906 philips pmbt3906 (1) monitor temperature from ?thermistor? the F81865 can connect two thermistors to me asure environment temperature or remote
F81865 may, 2010 v0.28p 45 temperature. the specification of t hermistor should be considered to (1) value is 3435k (2) resistor value is 10k ohm at 25 c. in the figure 7-1, the thermi stor is connected by a serial resistor with 10k ohm, then connected to vref. (2) monitor temperature from ?thermal diode? also, if the cpu, gpu or external circ uits provide thermal diode for temperature measurement, the F81865 is capable to these sit uations. the build-in reference table is for pnp 2n3906 transistor. in the figure 7-1, the transisto r is directly connected into temperature pins. adc noise filtering the adc is integrating type with inherently good noise rejection. micro-power operation places constraints on high-frequency noise reje ction; therefore, careful pcb board layout and suitable external filtering are required for high -accuracy remote measurement in electronically noisy environment. high frequency emi is best filter ed at d+ and d- with an external 2200pf or 3300pf capacitor. too high capacitance may introduce errors due to the rise time of the switched current source. nearly all noise sources test ed cause the adc measurement to be higher than the actual temperature, dependi ng on the frequency and amplitude. over temperature signal (ovt#) ovt# alert for temperature is shown as fi gure 7-3. when monitored temperature exceeds the over-temperature threshold val ue, ovt# will be asserted until the temperature goes below the hysteresis temperature. t hyst to ovt# (level mode) ovt# (smi mode) fig 7-3 temperature pme# pme# interrupt for temperature is shown as fi gure 7-4. temperature exceeding high limit or going below hysteresis will cause an interrupt if t he previous interrupt has been reset by writing ?1? all the interrupt status register.
F81865 may, 2010 v0.28p 46 *interrupt reset when interrupt status registers are written 1 to t hyst (pulse mode) * * fig 7-4 fan fan speed count inputs are provided by the signals from fans equipped with tachometer outputs. the level of these signals should be set to ttl level, and maximum input voltage cannot be over 5v. if the input signals from the tachometer output s are over the 5v, the external trimming circuit should be added to reduce the voltage to obtain the input specification. determine the fan counter according to: rpm 10 5 . 1 count 6 = in other words, the fan speed counter (12 bit resolution ) has been read from register, the fan speed can be evaluated by the following equation. count 10 5 . 1 rpm 6 = as for fan, it would be best to use 2 pulses ( 4 phases fan) tachometer output per round. so the parameter ?count? under 5 bit filter is 4096~64 and rpm is 366~23438 based on the above equation. if using 8 phases fan, rpm would be from 183~11719. fan speed control the F81865 provides 2 fan speed control methods: 1. dac fan control 2. pwm duty cycle
F81865 may, 2010 v0.28p 47 fanin monitor dc output voltage +12v r10k 1 2 3 jp1 con3 r 10k r 3.6k d1 1n4148 3 2 1 8 4 + - u1a lm358 r27k r 4.7k c 47u q1 pmos c 0.1u r 4.7k dac fan control the range of dc output is 0~vcc, controll ed by 8-bit register. 1 lsb is about 0.013v (vcc=3.3v). the output dc voltage is amplified by external op circuit, thus to reach maximum fan operation voltage, 12v. the output voltage will be given as followed: 256 value register 8bit programmed vcc (v) tage output_vol = and the suggested application circuit for linear fan control would be: fig 7-5 pwm duty fan control the duty cycle of pwm can be programmed by a 8- bit register. the default duty cycle is set to 100%, that is, the default 8-bit registers is set to ffh. the expression of duty can be represented as follows. % 100 255 value register 8bit programmed (%) duty_cycle =
F81865 may, 2010 v0.28p 48 +12v fan r1 r2 nmos pnp transisto r c + - d s g fig 7-6 fan speed control mechanism there are some modes to control fan speed and they are 1.manual mode, 2.stage auto mode, 3. linear auto mode. more detail, please refer the description of registers. manual mode for manual mode, it generally acts as software fan speed control. stage auto mode at this mode, the F81865 provides automatic fan speed control related to temperature variation of cpu/gpu or the system. the f 81865 can provide four temperature boundaries and five intervals, and each interval has its related fan speed count. all these values should be set by bios first. take figure 7-7 as example. when temperature boundaries are set as 45, 55, 65, and 75 c and there are five intervals (each interval is 10 c). the related desired fan speed counts for each interval are 0500h, 0400h, 0300h, 0200h and 0100h. when the temperature is within 55~65 c, the fan speed count 300h will be load into fan expect count that define in registers. then, the F81865 will adjust pwmout duty-cycle to meet the expected val ue. it can be said that the fan will be turned on with a specific speed set by bios and automatically controlled with the temperature variation. the F81865 will take charge of all the fan speed control and need no for software support. desired counts 0100h 0200h 0300h 0400h 0500h 75 degree c 65 degree c 55 degree c 45 degree c figure 7-7 there are some examples as below:
F81865 may, 2010 v0.28p 49 a. stage auto mode (pwm duty) set temperature as 60 c, 50 c, 40 c, 30 c and duty as 100%, 90%, 80%, 70%, 60% 100% 90% 80% 70% 60% 60 degree c 50 degree c 40 degree c 30 degree c 0xff 0xe5 0xcc 0xb2 0x99 ab cd temp. fan speed pwm duty hysteresis 47 degree c a. once temp. is under 30 c, the lowest fan speed keeps 60% pwm duty b. once temp. is over 30 c,40 c,50 c, the fan speed will vary from 60% to 90% pwm duty and increase with temp. level. c. once temp. keeps in 55 c, fan speed keeps in 90% pwm duty if set the hysteresis as 3 c (default 4 c), once temp reduces under 47 c, fan speed reduces to 80% pwm duty and stays there. b. stage auto mode (rpm%) set temperature as 60 c, 50 c, 40 c, 30 c and assume the full speed is 6000 rpm, set 90% of full speed rpm(5400 rpm), 80%(4800 rpm), 70%(4200 rpm), 60%(3600 rpm) of full speed rpm 6000rpm 90%(5400rpm) 80%(4800rpm) 70%(4200rpm) 60%(3600rpm) 60 degree c 50 degree c 40 degree c 30 degree c ab cd temp. fan speed hysteresis 47 degree c a. once temp. is under 30 c, the lowest fan speed keeps 60% of full speed (3600rpm). b. once temp. is over 30 c,40 c,50 c, the fan speed will vary from 3600rpm to 5400rpm and increase with temp. level. c. once temp. keeps in 55 c, fan speed keeps in 90% of full speed (5400rpm) d. if set the hysteresis as 3 c (default 4 c), once temp reduces under 47 c, fan speed reduces to 4800rpm and stays there. .
F81865 may, 2010 v0.28p 50 linear auto mode furthermore, F81865 also supports linear auto mo de. below two examples describe this mode. more detail, please refer to the register description. a. linear auto mode (pwm duty i) set temperature as 70 c, 60 c, 50 c, 40 c and duty as 100%, 70%, 60%, 50%, 40% 100% 70% 60% 50% 40% 70 degree c 60 degree c 50 degree c 40 degree c ab c d hysteresis 65 degree c temp. fan speed pwm duty a. once temp. is under 40 c, the lowest fan speed keeps 40% pwm duty b. once temp. is over 40 c,50 c,60 c, the fan speed will vary from 40% to 70% pwm duty and linearly increase with temp. variation. the temp.-fan speed monitoring and flash interval is 1sec. c. once temp. goes over 70 c, fan speed will directly increa se to 100% pwm duty (full speed) d. if set the hysteresis as 5 c(default is 4 c), once temp reduces under 65 c (not 70 c), fan speed reduces from 100% pwm duty and decrease linearly with temp.. b. linear auto mode (rpm%) set temperature as 70 c, 60 c, 50 c, 40 c and if full speed is 6000rpm, setting 100%, 70%, 60%, 50%, 40% of full speed. 6000rpm 70%(4200rpm) 60%(3600rpm) 50%(3000rpm) 40%(2400rpm) 70 degree c 60 degree c 50 degree c 40 degree c ab c d hysteresis 65 degree c temp. fan speed a. once temp. is under 40 c, the lowest fan speed keeps 40% of full speed (2400rpm) b. once temp. is over 40 c,50 c,60 c, the fan speed will vary from 40% to 70% of full speed and almost linearly increase with temp. variation. the temp.-fan speed monitoring and flash interval is 1sec.
F81865 may, 2010 v0.28p 51 c. once temp. goes over 70 c, fan speed will dire ctly increase to full speed 6000rpm. d. if set the hysteresis as 5 c, once temp reduces under 65 c (not 70 c), fan speed reduces from full speed and decrease linearly with temp.. pwmout duty-cycle operating process in both ?manual rpm? and ?temperature rpm? modes, the F81865 adjust pwmout duty-cycle according to current fan count and expect ed fan count. it will operate as follows: 1. when expected count is 0xfff, pwmout duty- cycle will be set to 0x00 to turn off fan. 2. when expected count is 0x000, pwmout duty-cycl e will be set to 0xff to turn on fan with full speed. 3. if both (1) and (2) are not true, when pwmout duty-cycle decrease to min_duty( 00h), obviously the duty-cycle will decrease to 00h next, the F81865 will keep duty-cy cle at 00h for 1.6 seconds. after that, the F81865 starts to compare current fan count and expected count in order to increase or decrease its duty-cycle. this ensures that if there is any glitch during the period, the F81865 will ignore it. start duty stop duty fig 7-8 fan_fault# fan_fault# will be asserted when the fan speed do esn?t meet the expected fan speed within a programmable period (default is 11 seconds) or when fan stops with respect to pwm duty-cycle which should be able to turn on the fan. there ar e two conditions may cause the fan_fault# event. (1). when pwm_duty reaches 0xff, the fan sp eed count can?t reach t he fan expected count on time. (figure 7-9) fan_fault# expected fan count 11 sec ( default ) current fan count duty-cycle 100% fig 7-9
F81865 may, 2010 v0.28p 52 (2). after the period of detecting fan full speed, when pwm_duty > min. duty, and fan count is still in 0xfff. 7.6.2 hardware moni tor device registers before the device registers, the following is a register map order which shows a summary of all registers. please refer each register if you want more detail information. register cr01 ~ cr0e ? configuration registers register cr10 ~ cr32 ? voltage setting register register cr60 ~ cr8f ? temperature setting register register cr90 ~ crbf ? fan control setting register ? fan1 detail setting cra0 ~ craf ? fan2 detail setting crb0 ~ crbf 7.6.2.1 configuration setting configuration register ? index 01h bit name r/w default description 7-3 reserved 0h 0 reserved 2 power_down r/w 0 hardware monitor function power down. 1 fan_start r/w 1 set one to enable startup of fan monito ring operations; a zero puts the part in standby mode. 0 v_t_start r/w 1 set one to enable startup of temperature and voltage monitoring operations; a zero puts the part in standby mode. configuration register ? index 02h bit name r/w default description 7 dummy_reg r/w 0 dummy register. 6 case_beep_en r/w 0 0: disable case open event output via beep. 1: enable case open event output via beep. 5-4 ovt_mode r/w 0 00: the ovt# will be level mode. 01: the ovt# will be 500us pulse mode (smi). 10: the ovt# will indicate by 1hz led function. 11: the ovt# will indicate by (400/800hz) beep output. 3 dummy_reg r/w 0 dummy register. 2 case_pme_en r / w 0 0: disable case open event output via pme. 1: enable case open event output via pme. 1-0 alert_mode r/w 0 00: the alert# will be low active level mode. 01: the alert# will be high active level mode. 10: the alert# will indicate by 1hz led function. 11: the alert# will indicate by (400/800hz) beep output. configuration register ? index 03h bit name r/w default description 7-1 reserved r/w 0 reserved 0 case_sts r/w 0 case open event status, wr ite 1 to clear if case open event cleared. cpu temperature measure method register ? index 0ah bit name r/w default description 7-6 reserved r/w 0 reserved. 5 t1_iir_en r/w 0 set one to enable the iir filter when cpu measure mode is peci
F81865 may, 2010 v0.28p 53 4 reserved r/w 0 reserved. 3-2 vtt_sel r/w 0 this register is used to select the output voltage for peci. 00: 1.23v 01: 1.13v 10: reserved. 11: 1.00v 1-0 meas_type r/w 0 this register selects the method fo r measuring the cpu temperature. 00: normal diode. 01: peci 10: reserved. 11: reserved. cpu select register ? index 0bh bit name r/w default description 7-4 cpu_sel r/w 0 each bit indicates one cpu. set only one bit at a time. 3-1 reserved r/w 0 reserved. 0 domain r/w 0 set one to enable getting dual core cpu temperature. tcc temperature register ? index 0ch bit name r/w default description 0 tcc_temp r/w 0x55 this indicates the tcc temperature for the peci. the absolute temperature is achieved by adding the reading from peci to this register. peci slope control register ? index 0eh bit name r/w default description 7-4 reserved - - reserved. 3 peci_add r/w 0 refer to peci_scale. 2-0 peci_scale r/w 0 this register accompany with peci_add defines the peci reading slope. (peci_read indicates the readi ng for host, peci_tmp indicates the reading from peci in the following description) when peci_add is 0: 000: peci_read = peci_tmp. 001: peci_read = peci_tmp - 1/2* (peci_tmp). 010: peci_read = peci_tmp - 1/4* (peci_tmp). 011: peci_read = peci_tmp - 1/8* (peci_tmp). 100: peci_read = peci_tmp - 1/16* (peci_tmp). 101: peci_read = peci_tmp - 1/32* (peci_tmp). 110: peci_read = peci_tmp - 1/64* (peci_tmp). 111: peci_read = peci_tmp - 1/128* (peci_tmp). when peci_add is 1: 000: peci_read = peci_tmp. 001: peci_read = peci_tmp + 1/2* (peci_tmp). 010: peci_read = peci_tmp + 1/4* (peci_tmp). 011: peci_read = peci_tmp + 1/8* (peci_tmp). 100: peci_read = peci_tmp + 1/16* (peci_tmp). 101: peci_read = peci_tmp + 1/32* (peci_tmp). 110: peci_read = peci_tmp + 1/64* (peci_tmp). 111: peci_read = peci_tmp + 1/128* (peci_tmp).
F81865 may, 2010 v0.28p 54 7.6.2.2 voltage setting voltage pme enable register ? index 10h bit name r/w default description 7-2 reserved r/w 0 reserved. 1 vin0_pme_en r/w 0 0: disable vin0 pme. 1: enable vin0 pme. see vin0_exc_sts for detail. 0 reserved r/w 0 reserved. voltage exceed status register ? index 11h bit name r/w default description 7-2 reserved r/w 0 reserved. 1 vin0_exc_sts r/w 0 this bit records the change of vin0 real time exceeding status. when vin0 exceeds vin0_high_limit or vin0 returns to the normal range, this bit will be set to ?1?. wr ite ?1? to clear this bit. 0 reserved r/w 0 return 0 when read. voltage real time exceed status register ? index 12h bit name r/w default description 7-2 reserved r/w 0 reserved. 1 vin0_exc r/w 0 0: vin0 is less or equal than vin0_high_limit. 1: vin0 is great than vin0_high_limit. 0 reserved r/w 0 return 0 when read. voltage beep enable register ? index 13h bit name r/w default description 7-2 reserved r/w 0 reserved. 1 vin0_beep_en r/w 0 0: disable vin0 beep. 1: enable vin0 beep. see vin0_exc for detail. 0 reserved r/w 0 reserved. voltage reading and limit ? index 20h- 2fh address attribute default value description 20h ro -- vcc3v reading. the unit of reading is 16mv. 21h ro -- vin0 (vcore) reading. the unit of reading is 8mv. 22h ro -- vin1 reading. the unit of reading is 8mv. 23h ro -- vin2 reading. the unit of reading is 8mv. 24h ro -- vin3 reading. the unit of reading is 8mv. 25h ro -- vsb3v reading. the unit of reading is 16mv. 26h ro -- vbat reading. the unit of reading is 16mv. 29~2fh ro ff reserved voltage vin0 high limit register ? index 32h bit name r/w default description 7-0 vin1_high_limit r/w ffh this defines the vin1 voltage high limit.
F81865 may, 2010 v0.28p 55 7.6.2.3 temperature setting temperature pme# enable register ? index 60h bit name r/w default description 7 reserved r/w 0 reserved 6 en_ t2_ ovt_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp2 exceeds ovt setting. 5 en_ t1_ ovt_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp1 exceeds ovt setting. 4 reserved r/w 0 reserved 3 reserved r/w 0 reserved 2 en_ t2_exc_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp2 exceeds high limit setting. 1 en_ t1_exc_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp1 exceeds high limit setting. 0 reserved r/w 0 reserved temperature interrupt status register ? index 61h bit name r/w default description 7 reserved - - reserved 6 t2_ovt _sts r/w 0 a one indicates temp2 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. writ e 1 to clear this bit, write 0 will be ignored. 5 t1_ovt _sts r/w 0 a one indicates temp1 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. writ e 1 to clear this bit, write 0 will be ignored. 4 reserved - - reserved 3 reserved - - reserved 2 t2_exc _sts r/w 0 a one indicates temp2 temperature sensor has exceeded high limit or below the ?high limit ?hysteresis? limit. write 1 to clear this bit, write 0 will be ignored. 1 t1_exc _sts r/w 0 a one indicates temp1 temperature s ensor has exceeded high limit or below the ?high limit ?hysteresis? limit. write 1 to clear this bit, write 0 will be ignored. 0 reserved - - reserved temperature real time status register ? index 62h bit name r/w default description 7 reserved r/w 0 reserved 6 t2_ovt r/w 0 set when the temp2 exceeds the ovt limit. clear when the temp2 is below the ?ovt limit ?hysteresis? temperature. 5 t1_ovt r/w 0 set when the temp1 exceeds the ovt limit. clear when the temp1 is below the ?ovt limit ?hysteresis? temperature. 4 reserved - - reserved 3 reserved - - reserved 2 t2_exc r/w 0 set when the temp2 exceeds the high limit. clear when the temp2 is below the ?high limit ?hysteresis? temperature. 1 t1_exc r/w 0 set when the temp1 exceeds the high limit. clear when the temp1 is below the ?high limit ?hysteresis? temperature. 0 reserved - - reserved
F81865 may, 2010 v0.28p 56 temperature beep enable register ? index 63h bit name r/w default description 7 reserved r/w 0 reserved 6 en_ t2_ ovt_beep r/w 0 if set this bit to 1, beep signal will be issued when temp2 exceeds ovt limit setting. 5 en_ t1_ ovt_beep r/w 0 if set this bit to 1, beep signal will be issued when temp1 exceeds ovt limit setting. 4 reserved r/w 0 reserved 3 reserved r/w 0 reserved 2 en_ t2_exc_beep r/w 0 if set this bit to 1, beep signal will be issued when temp2 exceeds high limit setting. 1 en_ t1_exc_beep r/w 0 if set this bit to 1, beep signal will be issued when temp1 exceeds high limit setting. 0 reserved r/w 0 reserved ovt output enable register 1 ? index 66h bit name r/w default description 7 reserved r 0h reserved. 6 en_t2_alert r/w 0 enable temperature alert (alert ) mechanism of temperature2. 5 en_t1_alert r/w 1 enable temperature alert (alert ) mechanism of temperature1. 4 reserved r 0h reserved. 3 reserved r 0h reserved. 2 en_t2_ovt r/w 0 enable over temperature (ovt ) mechanism of temperature2. 1 en_t1_ovt r/w 1 enable over temperature (ovt ) mechanism of temperature1. 0 reserved r 0h reserved. temperature sensor type register ? index 6bh bit name r/w default description 7-4 reserved ro 0 -- 3 reserved r 0h -- 2 t2_mode r/w 1 0: temp2 is connected to a thermistor. 1: temp2 is connected to a bjt. (default) 1 t1_mode r/w 1 0: temp1 is connected to a thermistor 1: temp1 is connected to a bjt.(default) 0 reserved r 0h -- temp1 limit hystersis sel ect register -- index 6ch bit name r/w default description 7-4 temp1_hys r/w 4h limit hysteresis. (0~15 c) temperature and below the (boundary ? hysteresis). 3-0 reserved r 0h -- temp2 limit hystersis sel ect register -- index 6dh bit name r/w default description 7-4 reserved r 0h -- 3-0 temp2_hys r/w 4h limit hysteresis. (0~15 c) temperature and below the (boundary ? hysteresis).
F81865 may, 2010 v0.28p 57 diode open status register -- index 6fh bit name r/w default description 7-4 reserved ro 0h reserved 3 reserved ro 0h reserved 2 t2_diode_open ro 0h external diode 2 is open 1 t1_diode_open ro 0h external diode 1 is open 0 reserved r 0h -- temperature ? index 70h- 8fh address attribute default value description 70h reserved -- reserved 71h reserved -- reserved 72h ro -- temperature 1 reading (temp1). the unit of reading is 1 o c.at the moment of reading this register. 73h reserved -- reserved 74h ro -- temperature 2 reading (temp2). the unit of reading is 1 o c.at the moment of reading this register. 75h reserved -- reserved 76h reserved -- reserved 77-7bh reserved -- reserved 7c-7fh reserved -- reserved 80h reserved -- reserved 81h reserved -- reserved 82h r/w 64h temperature sensor 1 ovt limit. the unit is 1 o c. 83h r/w 55h temperature sensor 1 high limit. the unit is 1 o c. 84h r/w 64h temperature sensor 2 ovt limit. the unit is 1 o c. 85h r/w 55h temperature sensor 2 high limit. the unit is 1 o c. 86h reserved -- reserved 87h reserved -- reserved 88-8bh reserved -- reserved 8c~8fh reserved -- reserved 7.6.2.4 fan control setting fan pme# enable register ? index 90h bit name r/w default description 7-2 reserved ro 0h reserved 1 en_fan2_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for fan2.
F81865 may, 2010 v0.28p 58 0 en_fan1_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for fan1. fan interrupt status register ? index 91h bit name r/w default description 7-2 reserved ro 0 reserved 1 fan2_sts r/w -- this bit is set when the fan2 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 0 fan1_sts r/w -- this bit is set when the fan1 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. fan real time status register ? index 92h bit name r/w default description 7-2 reserved -- 0 reserved 1 fan2_exc ro -- this bit set to high mean that fan2 count can?t meet expect count over than pme time(cr9f) or when duty not ze ro but fan stop over then 3 sec. 0 fan1_exc ro -- this bit set to high mean that fan1 count can?t meet expect count over than pme time(cr9f) or when duty not ze ro but fan stop over then 3 sec. fan beep# enable register ? index 93h bit name r/w default description 7 reserved r/w 0 reserved 6 full_with_t2_en r/w 0 set this bit to one will trig all fans to full speed when t2 is over the high limit. 5 full_with_t1_en r/w 0 set this bit to one will trig all fans to full speed when t1 is over the high limit. 4 reserved r/w 0 reserverd 3 reserved ro 0 reserved 2 reserved ro 0 reserved 1 en_fan2_ beep r/w 0 a one enables the corresponding interrupt status bit for beep. 0 en_fan1_ beep r/w 0 a one enables the corresponding interrupt status bit for beep. fan type select register -- index 94h bit name r/w default description 7-6 reserved -- -- reserved. 5-4 reserved -- -- reserved 3-2 fan2_type r/w 2?b 0s 00: output pwm mode (pushpull) to control fans. 01: use linear fan application circuit to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. 1-0 fan1_type r/w 2?b 0s 00: output pwm mode (push pull) to control fans. 01: use linear fan application circuit to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. s : register default values are decided by trapping. fan mode select register -- index 96h bit name r/w default description 7-6 reserved -- -- reserved
F81865 may, 2010 v0.28p 59 5-4 reserved -- -- reserved 3-2 fan2_mode r/w 1h 00: auto fan speed control, fan spee d will follow different temperature by different rpm that define in 0xb6-0xbe. 01: auto fan speed control, fan spee d will follow different temperature by different duty cycle (voltage) that defined in 0xb6-0xbe. 10: manual mode fan control, user can write expect rpm count to 0xb2-0xb3, and F81865 will auto contro l duty cycle (pwm fan type) or voltage (linear fan type) to control fan speed. 11: manual mode fan control, user can write expected duty cycle (pwm fan type) or voltage (linear fan type) to 0xb3, it will output that value duty or voltage to controlled fan speed. 1-0 fan1_mode r/w 1h 00: auto fan speed control, fan spee d will follow different temperature by different rpm that define in 0xa6-0xae. 01: auto fan speed control, fan spee d will follow different temperature by different duty cycle that defined in 0xa6-0xae. 10: manual mode fan control, user can write expect rpm count to 0xa2-0xa3, and F81865 will auto contro l duty cycle (pwm fan type) or voltage (linear fan type) to control fan speed. 11: manual mode fan control, user can write expected duty cycle (pwm fan type) or voltage (linear fan type) to 0xa3, it will output that value duty or voltage to control fan speed. auto fan1 and fan2 boundary hystersis select register -- index 98h bit name r/w default description 7-4 fan2_hys r/w 4h 0000: boundary hysteresis. (0~15 degree c) segment will change when the temperature over the boundary temperature and below the (boundary ? hysteresis ). 3-0 fan1_hys r/w 4h 0000: boundary hysteresis. (0~15 degree c) segment will change when the temperature over the boundary temperature and below the (boundary ? hysteresis ). auto fan1 and fan2 update rate select register -- index 9bh bit name r/w default description 7-6 reserved -- -- reserved 5-4 reserved -- -- reserved 3-2 fan2_rate_sel r/w 01 fan2 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 1-0 fan1_rate_sel r/w 01 fan1 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz fan1 and fan2 start up duty-cycle/voltage ? index 9ch bit name r/w default description 7-4 fan2_stop_duty r/w 5h when fan start, the fan_ctrl2 will increase duty-cycle from 0 to this (value x 8) directly. and if fan speed is down, the fan_ctrl 2 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4).
F81865 may, 2010 v0.28p 60 3-0 fan1_stop_duty r/w 5h when fan start, the fan_ctrl 1 will increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fan_ctrl 1 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). fan fault time register -- index 9fh bit name r/w default description 7-5 reserved -- -- reserved. 4 start_duty_sel r/w -- 0: the power on fan speed is 100% 1: the power on fan speed is 60%. this bit is power on trap by fan_100_60. default is 60%. 3-0 fan_pme_time r/w 0ah this is the time value in second for the fan fault mechanism. if the duty is 100% in rpm mode and the fan speed can?t exceed the expected value. after the time set by this byte, the fan fault will asserts if it is enabled. fan1 index a0h- afh address attribute default value description a0h ro 8?h0f fan1 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a1h ro 8?hff fan1 count reading (lsb). a2h~ a3h reserved -- see index 96h a4h r/w 8?h03 fan1 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prev ent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a5h r/w 8?hff fan1 full speed count reading (lsb). t1 boundary 1 temperature ? index a6h bit name r/w default description 7 reserved ro 0 reserved 6-0 bound1tmp1 r/w 3ch (60 o c) the 1 st boundary temperature for vt1 in temperature mode. when t1 temperature exceeds this boundary, fan1 expect value will be in full speed. when vt1 temperature is below this boundary ? hysteresis, fan1 expect value will load the value calcul ated from segment2 index abh. t1 boundary 2 temperature ? index a7 bit name r/w default description 7 reserved ro 0 reserved 6-0 bound2tmp1 r/w 32h (50 o c) the 2nd boundary temperature for vt1 in temperature mode. when t1 temperature exceeds this boundary, fan1 expect value will load from segment 2 register (index abh). when t1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 3 register (index ach). t1 boundary 3 temperature ? index a8h bit name r/w default description 7 reserved ro 0 reserved.
F81865 may, 2010 v0.28p 61 6-0 bound3tmp1 r/w 28h (40 o c) the 3rd boundary temperature fo r vt1 in temperature mode. when t1 temperature exceeds this boundary, fan1 expect value will load from segment 3 register (index ach). when t1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 4 register (index adh). t1 boundary 4 temperature ? index a9 bit name r/w default description 7 reserved ro 0 reserved. 6-0 bound4tmp1 r/w 1eh (30 o c) the 4 th boundary temperature for vt1 in temperature mode. when t1 temperature exceeds this boundary, fan1 expect value will load the value calculated from segment 4 (index adh). when t1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 5 register (index aeh). fan1 segment 1 speed count ? index aah bit name r/w default description 7-0 seg1speed1 r/w ffh (100%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 2 speed count ? index abh bit name r/w default description 7-0 seg2speed1 r/w d9h (85%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 3 speed count ? index ach bit name r/w default description 7-0 seg3speed1 r/w b2h (70%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 4 speed count ? index adh bit name r/w default description 7-0 seg4speed1 r/w 99h (60%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
F81865 may, 2010 v0.28p 62 fan1 segment 5 speed count ? index aeh bit name r/w default description 7-0 seg5speed1 r/w 80h (50%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 temperature mapping select ? index afh bit name r/w default description 7-6 reserved -- 0 reserved 5 fan1_up_t_en r / w 0 0: fan1 speed still follows the t1. 1: fan1 will load the full speed when any temperature exceeds its high limit. 4 fan1_interpolation_ en r/w 1 0: when t1 is in the range between bound1tmp1 and bound4tmp1, t h e f a n e x p e c t i s seg2speed1. 1: when t1 is in the range between bound1tmp1 and bound4tmp1, the fan expect is calc ulated by the equation: fan expect = [(current temp ? bound4tmp1)/(boudn1tmp1 ? bound4tmp1)]*(seg2speed1 ? seg5speed1) + seg5speed1. 3 fan1_jump_high_en r / w 1 0: when t1 is over bound1tmp1, the duty cycle will increase one by one. 1: when t1 is over bound1tmp1, the duty cycle will directly jump to full speed. 2 fan1_jump_low_en r/w 1 0: when t1 is over bound1tmp1, the duty cycle will decrease one by one. 1: when t1 is over bound1tmp1, the duty cycle will directly jump to the expect value. 1-0 fan1_temp_sel r/w 1 0: reserved. 1: fan1 follow temperature 1. 2: fan1 follow temperature 2. 3: reserved. fan2 index b0h- bfh address attribute default value description b0h ro 8?h0f fan2 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b1h ro 8?hff fan2 count reading (lsb). b2h~b3h reserved -- see index 96h b4h r/w 8?h03 fan2 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prev ent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b5h r/w 8?hff fan2 full speed count reading (lsb). t2 boundary 1 temperature ? index b6h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound1tmp2 r/w 3ch (60 o c) the 1 st boundary temperature for vt2 in temperature mode. when t1 temperature exceeds this boundary, fan2 expect value will be in full speed. when t2 temperature is below this boundary ? hysteresis, fan2 expect value will load the value calculated from segment2 (index bbh).
F81865 may, 2010 v0.28p 63 t2 boundary 2 temperature ? index b7 bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound2tmp2 r/w 32 (50 o c) the 2nd boundary temperature for vt2 in temperature mode. when t2 temperature exceeds this boundary, fan2 expect value will load from segment 2 register (index bbh). when t2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 3 register (index bch). t2 boundary 3 temperature ? index b8h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound3tmp2 r/w 28h (40 o c) the 3rd boundary temperature fo r vt2 in temperature mode. when t2 temperature exceeds this boundary, fan2 expect value will load from segment 3 register (index bch). when t2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 4 register (index bdh). t2 boundary 4 temperature ? index b9 bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound4tmp2 r/w 1eh (30 o c) the 4 th boundary temperature for vt2 in temperature mode. when t2 temperature exceeds this boundary, fan2 expect value will load the value calculated from segment2 (index bdh). when t2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 5 register (index beh). fan2 segment 1 speed count ? index bah bit name r/w default description 7-0 seg1speed2 r/w ffh (100%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: 100%: full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ( (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 2 speed count ? index bbh bit name r/w default description 7-0 seg2speed2 r/w d9h (85%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 3 speed count ? index bch bit name r/w default description 7-0 seg3speed2 r/w b2h (70%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
F81865 may, 2010 v0.28p 64 fan2 segment 4 speed count ? index bdh bit name r/w default description 7-0 seg4speed2 r/w 99h (60%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 5 speed count ? index beh bit name r/w default description 7-0 seg5speed2 r/w 80h (50%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 temperature mapping select ? index bfh bit name r/w default description 7-6 reserved -- 0 reserved 5 fan2_up_t_en r/w 0 0: fan2 speed still follows the t2. 1: fan2 will load the full speed when any temperature exceeds its high limit. 4 fan2_interpolati on_en r/w 1 0: when t2 is in the range between bound1tmp2 and bound4tmp2, the fan expect is seg2speed2. 1: when t2 is in the range between bound1tmp2 and bound4tmp2, the fan expect is calc ulated by the equation: fan expect = [(current temp ? bound4tmp2)/(boudn1tmp2 ? bound4tmp2)]*(seg2speed2 ? seg5speed2) + seg5speed2. 3 fan2_jump_high_ en r/w 1 0: when t2 is over bound1tmp2, the duty cycle will increase one by one. 1: when t2 is over bound1tmp2, the duty cycle will directly jump to full speed. 2 fan2_jump_low_ en r/w 1 0: when t2 is over bound1tmp2, the duty cycle will decrease one by one. 1: when t2 is over bound1tmp2, the duty cycle will directly jump to the expect value. 1-0 fan2_temp_sel r/w 2 0: reserved. 1: fan1 follow temperature 1. 2: fan1 follow temperature 2. 3: reserved. 7.7. spi interface communication between the two devices is handling via the serial peripheral interface (spi). every spi system consist of one master and one or more slaves, where a master provides the spi clock and slave receives clock from the master. this design is only master function, for basic signal, master-out/slave-in (mosi), master-in/slave-out (miso), seri al clock (sck), and 2 slaves se lect (ss), are needed for spi interface. each of slave select supports from 512k bits to 8mbits flash is decided by configuration register. serial clock (sck) signal frequency is varied from 1.7mhz to 33mhz. the serial data (mosi) for spi interface translates to depend on sck rising edge or falling edge is decided by
F81865 may, 2010 v0.28p 65 configuration register. 7.8. acpi function the advanced configuration and power interface (a cpi) is a system for controlling the use of power in a computer. it lets computer manufacture r and user to determine the computer?s power usage dynamically. there are three acpi states that are of primar y concern to the system designer and they are designated s0, s3 and s5. s0 is a full-power state; the computer is being actively used in this state. the other two are called sleep states and reflect differ ent power consumption when power-down. s3 is a state that the processor is powered down but the last procedural state is being stored in memory which is still active. s5 is a state that memory is off and the last procedural state of the processor has been stored to the hard disk. take s3 and s5 as comparison, si nce memory is fast, the computer can quickly come back to full-power state, the disk is slower than the memory and the computer takes longer time to come back to full-power state. however, since the memory is off, s5 draws the minimal power comparing to s0 and s3. there are 4 modes under power loss state via setti ng acpi control register. the always on, always off, keep last state & bypass mode.. in keep last state mode, one register will latch the status before power loss. if it is power on before po wer loss, it will automatically power on when power is resumed. if it is power off before power loss, it will remain power off when power is resumed. pwrok signals vdd3vok atxpwgd pwrok delay pwrok is delayed 400ms (default) as vcc arrives 2.8v, and the delay timing can be programmed via register (100ms ~ 400ms). 7.9. watchdog timer function watch dog timer is provided for system controlling. if time -out can trigger one signal to high/low level/pulse, the signal is depend on register setting. the time unit has two ways from 1sec or 60sec. in pulse mode, there are four pulse widths can be selected (1ms/25ms/125ms/5sec). others, please refer the device register description as below. watchdog timer configuration register 1 ? base address + 05h bit name r/w default description 7 reserved r 0 reserved 6 wdtmout_sts r/w 0 if watchdog timeout event occurs, this bit will be set to 1. write a 1 to this bit will clear it to 0.
F81865 may, 2010 v0.28p 66 5 wd_en r/w 0 if this bit is set to 1, the counting of watchdog time is enabled. 4 wd_pulse r/w 0 select output mode (0: level, 1: pulse) of rstout# by setting this bit. 3 wd_unit r/w 0 select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit. 2 wd_hactive r/w 0 select output polarity of rstout# (1: high active, 0: low active) by setting this bit. 1-0 wd_pswidth r/w 0 select output pulse width of rstout# 0: 1 ms 1: 25 ms 2: 125 ms 3: 5 sec watchdog timer configuration register 2 ? base address + 06h bit name r/w default description 7-0 wd_time r/w 0 time of watchdog timer watchdog pme control register ? base address + 0ah bit name r/w default description 7 wdt_pme r -- the pme status. this bit will set when wdt_pme_en is set and the watchdog timer is 1 unit before time out (or time out). 6 wdt_pme_en r/w 0 0: disable watchdog pme. 1: enable watchdog pme. 5-1 reserved -- -- reserved. 0 wdout_en r/w 0 0: disable watchdog time out output via wdtrst#. 1: enable watchdog time out output via wdtrst#. 7.10. rtc function the rtc function is a full binary-coded decimal (bcd) low-power real time clock and calendar chip which provides seconds, minutes, hours, day, date, month, and year information. functions can be upgraded flexibly for special mb system. more detail description and setting, please refer to the device register as below. seconds register ? index 00h bit name r/w default description 7 reserved r 0 reserved 6-0 sec r/w 00h seconds (sec). to write this sec, ?set? bit (cr0b[7]) must be set to 1. seconds alarm register ? index 01h bit name r/w default description 7 sec_alarm_en r/w 0 seconds alarm enable (sec_alarm_en). to compare sec_alarm with sec, this bi t must be set to 1. if this bit is not set to 1, it means that you don?t care about second alarm. 6-0 sec_alarm r/w 00h seconds alarm (sec_alarm). minutes register ? index 02h bit name r/w default description 7 reserved r 0 reserved 6-0 min r/w 00h minutes (min). to write min, ?set? bit ( cr0b[7]) must be set to 1.
F81865 may, 2010 v0.28p 67 minutes alarm register ? index 03h bit name r/w default description 7 min_alarm_en r/w 0 minutes alarm enable. to compare min_alarm with min, this bi t must be set to 1. if this bit is not set to 1, it means that you don?t care about minutes alarm. 6-0 min_alarm r/w 00h minutes alarm (min_alarm). hours register ? index 04h bit name r/w default description 7 pm_flag r/w 0 pm flag (pm_flag) this bit is used to indicate that hour is at am or pm. it only makes sense when ?m24? bit (cr0c[1]) is set to 0. to write this bit, ?set? bit (cr0c[7]) must be set to 1. 0: am 1: pm 6 reserved r 0 reserved 5-0 hrs r/w 12h hours (hrs). to write hrs, ?set? bit (cr0c[7]) must be set to 1. hours alarm register ? index 05h bit name r/w default description 7 hrs_alarm_en r/w 0 hours alarm enable (hrs_alarm_en) to compare hrs_alarm/pm_alarm with hrs/pm_flag, this bit must be set to 1. if this bit is not set to 1, it means that y ou don?t care about hours alarm. 6 pm_alarm r/w 0 pm flag alarm (pm_alarm) 5-0 hrs_alarm r/w 00h hours alarm (hrs_alarm). day of week register ? index 06h bit name r/w default description 7-3 reserved r 0 reserved 2-0 week r/w 001b day of week (week). to write week, ?set? bit (cr0c[7]) must be set to 1. 001: sunday 010: monday 011: tuesday 100: wednesday 101: thursday 110: friday 111: saturday date of month register ? index 07h bit name r/w default description 7-6 reserved r 0 reserved 5-0 dom r/w 01h date of month (dom). to write dom, ?set? bit ( cr0c[7]) must be set to 1. month register ? index 08h bit name r/w default description 7-5 reserved r 0 reserved 4-0 mth r/w 01h month (mth). to write mth, ?set? bit (cr0c[7]) must be set to 1.
F81865 may, 2010 v0.28p 68 year register ? index 09h bit name r/w default description 7-0 year r/w 07h year (year) to write year, ?set? bit (cr0c[7]) must be set to 1. control register 1 ? index 0ah bit name r/w default description 7 uip r 0 update cycle in progress (uip). uip is cleared in the end of an update cycle and when ?set? (cr0c[7]) is 1. 6-4 reserved r/w 010b reserved 3-0 pir r/w 0000b periodic interru pt rate (pir) 0000: none 0001: 16 khz 0010: 8 khz 0011: 4 khz 0100: 2 khz 0101: 1 khz 0110: 512 hz 0111: 256 hz 1000: 128 hz 1001: 64 hz 1010: 32 hz 1011: 16 hz 1100: 8 hz 1101: 4 hz 1110: 2 hz 1111: 1 hz control register 2 ? index 0bh bit name r/w default description 7 set r/w 0 set calendar registers (set) this bit must be set to 1 to enable writing calendar registers. when this bit is set, the calendar update process will be stop. 6 pie r/w 0 periodic interrupt enable (pie) the bit is set to 1 to enable the generation of interrupt by pf (cr0e[6]). 5 aie r/w 0 alarm interrupt enable (aie) this bit is set to 1 to enable the ge neration of interrupt by uf (cr0e[5]). 4 uie r/w 0 update-ended interrupt enable (uie) this bit is set to 1 to enable the ge neration of interrupt by uf (cr0e[4]) 3 reserved r 0 reserved 2 dm r/w 0 data mode (dm) 0: binary coded decimal mode (bcd mode) 1: binary mode 1 m24 r/w 0 24/12 hours mode (m24) 0: am/pm 12 hours mode 1: 24 hours mode 0 dse r/w 0 daylight saving enable (dse) 0: disable special updates 1: enable special updates: (a) the last sunday of april, the time increases from am 01:59:59 to am 03:00:00. (b) the last sunday of october, t he time decreases from am 01:59:59 to am 01:00:00
F81865 may, 2010 v0.28p 69 status register ? index 0ch bit name r/w default description 7 rtc_int_n r 1 rtc interrupt request flag (rtc_int_n). the interrupt request flag is set to 0 if one of the following cases are true: fp*pie = ?1? af*aie = ?1? uf*uie = ?1? 6 pf r 0 periodic interrupt flag (pf) this bit is set to 1 when a rising edge is detected on the selected pir clock. pf is set to 1 regardless of t he state of pie bit. this bit is cleared after cr0e is read. 5 af r 0 alarm interrupt flag (af) this bit is set to 1 when the current time has reached the alarm time. af is set to 1 regardless of the state of aie bit. this bit is cleared after cr0e is read. 4 uf r 0 update-ended interrupt flag (uf) this bit is set to 1 after the end of each update cycle. uf is set to 1 regardless of the state of uie bit. this bit is cleared after cr0e is read. 3-0 reserved r 0 reserved data valid register ? index 0dh bit name r/w default description 7 data_valid r 1 data valid flag (data_valid) read this bit in lsh0051a will always return 1. 6 dom_alarm_en r/w 0 date of month alarm enable (dom_alarm_en). to compare dom_alarm with dom, this bi t must be set to 1. if this bit is not set to 1, it means that you don ?t care about date of month alarm. 5-0 dom_alarm r/w 00h date of month alarm (dom_alarm). ram data register ? index 0eh ~ indexffh (total 242 bytes) 8. register description the configuration register is used to control the behavior of the corresp onding devices. to configure the register, using the index port to select the index and then writing da ta port to alter the parameters. the default index port and data port are 0x4e and 0x4f respectively. pull down the sout1 pin to change the default value to 0x2e/0x2f. to enable configuration, the entry key 0x87 mu st be written to the index port. to disabl e configuration, write exit key 0xaa to the index port. following is a example to enable co nfiguration and disable conf iguration by using debug. -o 4e 87 -o 4e 87 ( enable configuration ) -o 4e aa ( disable configuration ) the following is a register map (total devices) grouped in hexadecimal address order, which shows a summary of all registers and their default value. please refer to eac h device chapter if you want more detail information.
F81865 may, 2010 v0.28p 70 global control registers ?-? reserved or tri-state global control registers register 0x[hex] register name default value msb lsb 02 software reset register - - - - - - - 0 07 logic device number register (ldn) 0 0 0 0 0 0 0 0 20 chip id register 0 0 0 0 0 1 1 1 21 chip id register 0 0 0 0 0 1 0 0 23 vender id register 0 0 0 1 1 0 0 1 24 vender id register 0 0 1 1 0 1 0 0 25 i2c address select register 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 26 clock select register 0 - - 0 - - - 0 27 rom address select register 0 0/1 1/0 1/0 0/1 0/1 0/1 0 28 gpio4 enable register 0 0 0 0 0 0 0 0 29 gpio3 enable register 0 0 0 0 0 0 0 0 2a-1 led mode select register 0 0 0 0 0 0 0 0 2a-2 full ur5 ur6 select - - - - 0 0 0 0 2b gpio1 enable register 0 0 0 1 1 1 1 1 2c gpio2 enable register 0 0 0 0 0 0 0 0 2d wakeup control register 0 - - - 1 0 0 0 device configuration registers ?-? reserved or tri-state fdc device configuration registers (ldn cr00) register 0x[hex] register name default value msb lsb 30 fdc device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1 61 base address low register 1 1 1 1 0 0 0 0 70 irq channel select register - - - - 0 1 1 0 74 dma channel select register - - - - - 0 1 0 f0 fdd mode register - - - 0 1 1 1 0 f2 fdd drive type register - - - - - - 1 1 f4 fdd selection register - - - 0 0 - 0 0 parallel port device config uration registers (ldn cr03) register 0x[hex] register name default value msb lsb
F81865 may, 2010 v0.28p 71 30 parallel port device enabl e register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1 61 base address low register 0 1 1 1 1 0 0 0 70 irq channel select register - - - - 0 1 1 1 74 dma channel select register - - - 0 - 0 1 1 f0 prt mode select register - 1 0 0 0 0 1 0 hardware monitor device conf iguration registers (ldn cr04) register 0x[hex] register name default value msb lsb 30 h/w monitor device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 0 61 base address low register 1 0 0 1 0 1 0 1 70 irq channel select register - - - - 0 0 0 0 kbc device configuration registers (ldn cr05) register 0x[hex] register name default value msb lsb 30 kbc device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 1 1 0 0 0 0 0 70 kb irq channel select register - - - - 0 0 0 0 72 mouse irq channel select register - - - - 0 0 0 0 fe ps/2 swap register 0 - - 0 0 0 0 1 f0 user wakeup code 0 1 1 1 0 0 0 1 gpio device configuration registers (ldn cr06) register 0x[hex] register name default value msb lsb 30 h/w monitor device enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 1 1 0 0 0 0 0 70 irq channel select register - - - - 0 0 0 0 f1 gpio0 output data register 0 0 0 0 0 0 0 0 f2 gpio0 pin status register - - - - - - - - f3 gpio0 drive enable register 0 0 0 0 0 0 0 0 f4 gpio0 mode select 1 register 0 0 0 0 0 0 0 0 f5 gpio0 mode select 2 register 0 0 0 0 0 0 0 0 f6 gpio0 pulse width select 1 register 0 0 0 0 0 0 0 0 f7 gpio0 pulse width select 2 register 0 0 0 0 0 0 0 0 f8 gpio0 interrupt enable register 0 0 0 0 0 0 0 0
F81865 may, 2010 v0.28p 72 f9 gpio0 interrupt status register 0 0 0 0 0 0 0 0 e0 gpio1 output enable register 0 0 0 0 0 0 0 0 e1 gpio1 output data register 1 1 1 1 1 1 1 1 e2 gpio1 pin status register - - - - - - - - e3 gpio1 drive enable register 0 0 0 0 0 0 0 0 ef led mode register 0 - - - 0 0 0 0 d0 gpio2 output enable register 0 0 0 0 0 0 0 0 d1 gpio2 output data register 1 1 1 1 1 1 1 1 d2 gpio2 pin status register - - - - - - - - d3 gpio2 drive enable register 0 0 0 0 0 0 0 0 c0 gpio3 output enable register 0 0 0 0 0 0 0 0 c1 gpio3 output data register 1 1 1 1 1 1 1 1 c2 gpio3 pin status register - - - - - - - - c3 gpio3 drive enable register 0 0 0 0 0 0 0 0 b0 gpio4 output enable register 0 0 0 0 0 0 0 0 b1 gpio4 output data register 1 1 1 1 1 1 1 1 b2 gpio4 pin status register - - - - - - - - b3 gpio4 drive enable register 0 0 0 0 0 0 0 0 a0 gpio5 output enable register 0 0 0 0 0 0 0 0 a1 gpio5 output data register 1 1 1 1 1 1 1 1 a2 gpio5 pin status register - - - - - - - - a3 gpio5 drive enable register 0 0 0 0 0 0 0 0 90 gpio6 output enable register - - - 0 0 0 0 0 91 gpio6 output data register - - - 1 1 1 1 1 92 gpio6 pin status register - - - - - - - - 93 gpio6 drive enable register - - - 0 0 0 0 0 wdt device configuration registers (ldn cr07) register 0x[hex] register name default value msb lsb 30 wdt device enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 0 0 0 0 0 0 0 f5 wdt control register 0 0 0 0 0 0 0 0 f6 wdt timer register 0 0 0 0 0 0 0 0 fa wdt pme enable register 0 0 - - - - - 0 spi device configuration registers (ldn cr08) register 0x[hex] register name default value msb lsb
F81865 may, 2010 v0.28p 73 f0 spi control register 0 0 0 1 0 0 0 0 f1 spi timeout value register 0 0 0 0 0 1 0 0 f2 spi baud rate divisor register - - - - - 0 0 1 f3 spi status register 0 - - - 0 - - - f4 spi high byte data register 0 0 0 0 0 0 0 0 f5 spi command data register 0 0 0 0 0 0 0 0 f6 spi chip select register - - - - 0 0 0 0 f7 spi memory mapping register - - - - - - - - f8 spi operate register 0 0 0 0 0 0 0 0 fa spi low byte data register 0 0 0 0 0 0 0 0 fb spi address high byte register 0 0 0 0 0 0 0 0 fc spi address medium byte register 0 0 0 0 0 0 0 0 fd spi address low byte register 0 0 0 0 0 0 0 0 fe spi program byte register 0 0 0 0 0 0 0 0 ff spi write data register 0 0 0 0 0 0 0 0 pme and acpi device configuration registers (ldn cr0a) register 0x[hex] register name default value msb lsb 30 rtc device enable register - - - - - - - 0 f0 pme event enable 1 register - 0 0 0 0 0 0 0 f1 pme event enable 2 register - - 0 0 0 0 0 0 f2 pme event status 1 register - - - - - - - - f3 pme event status 2 register - - - - - - - - f4 acpi control register 0 0 0 0 0 1 1 0 f5 acpi control register - 0 0 1 1 1 0 0 f6 acpi control register 0 0 0 0 0 0 0 0 rtc device configuration registers (ldn cr0b) register 0x[hex] register name default value msb lsb 30 rtc device enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 0 0 0 0 0 0 0 70 irq channel select register - - - - 0 0 0 0 uart1 device configuration registers (ldn cr10) register 0x[hex] register name default value msb lsb 30 device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1
F81865 may, 2010 v0.28p 74 61 base address low register 1 1 1 1 1 0 0 0 70 irq channel select register - - - - 0 1 0 0 f0 control register 0 0 0 0 - - 0 0 f2 clock select register - - - - - - 0 0 f4 slave address register 0 0 0 0 0 0 0 0 f5 slave address enable register 0 0 0 0 0 0 0 0 uart2 device configuration registers (ldn cr11) register 0x[hex] register name default value msb lsb 30 device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 0 61 base address low register 1 1 1 1 1 0 0 0 70 irq channel select register - - - - 0 0 1 1 f0 control register 0 0 0 0 - - 0 0 f2 clock select register - - - - - - 0 0 f4 slave address register 0 0 0 0 0 0 0 0 f5 slave address enable register 0 0 0 0 0 0 0 0 uart3 device configuration registers (ldn cr12) register 0x[hex] register name default value msb lsb 30 device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1 61 base address low register 1 1 1 0 1 0 0 0 70 irq channel select register - - - - 0 1 0 0 f0 control register 0 0 0 0 - - 0 0 f2 clock select register - - - - - - 0 0 f4 slave address register 0 0 0 0 0 0 0 0 f5 slave address enable register 0 0 0 0 0 0 0 0 uart4 device configuration registers (ldn cr13) register 0x[hex] register name default value msb lsb 30 device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 0 61 base address low register 1 1 1 0 1 0 0 0 70 irq channel select register - - - - 0 0 1 1 f0 control register 0 0 0 0 - - 0 0 f2 clock select register - - - - - - 0 0 f4 slave address register 0 0 0 0 0 0 0 0
F81865 may, 2010 v0.28p 75 f5 slave address enable register 0 0 0 0 0 0 0 0 uart5 device configuration registers (ldn cr14) register 0x[hex] register name default value msb lsb 30 device enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 0 0 0 0 0 0 0 70 irq channel select register - - - - 0 0 0 0 f0 control register 0 0 0 0 - - 0 0 f2 clock select register - - - - - - 0 0 f4 slave address register 0 0 0 0 0 0 0 0 f5 slave address enable register 0 0 0 0 0 0 0 0 uart6 device configuration registers (ldn cr15) register 0x[hex] register name default value msb lsb 30 device enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 0 0 0 0 0 0 0 70 irq channel select register - - - - 0 0 0 0 f0 control register 0 0 0 0 0 0 0 0 f1 ir mode register - - - 0 0 0 0 0 f2 clock select register - - - - - - 0 0 f4 slave address register 0 0 0 0 0 0 0 0 f5 slave address enable register 0 0 0 0 0 0 0 0 8.1 global control registers 8.1.1 software reset register ? index 02h bit name r/w default description 7-1 reserved - - reserved 0 soft_rst r/w 0 write 1 to reset the r egister and device powered by vdd (vcc).
F81865 may, 2010 v0.28p 76 8.1.2 logic device number register (ldn) ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select fdc device c onfiguration registers. 03h: select parallel port devic e configuration registers. 04h: select hardware monitor device configuration registers. 05h: select kbc device c onfiguration registers. 06h: select gpio device c onfiguration registers. 07h: select wdt device configuration registers. 08h: select spi device c onfiguration registers. 0ah: select pme & acpi devic e configuration registers. 0bh: select rtc device c onfiguration registers. 10h: select ur1 device c onfiguration registers. 11h: select ur2 device c onfiguration registers. 12h: select ur3 device c onfiguration registers. 13h: select ur4 device c onfiguration registers. 14h: select ur5 device c onfiguration registers. 15h: select ur6 device c onfiguration registers. 8.1.3 chip id register ? index 20h bit name r/w default description 7-0 chip_id1 r 07h chip id 1. 8.1.4 chip id register ? index 21h bit name r/w default description 7-0 chip_id2 r 04h chip id2. 8.1.5 vendor id register ? index 23h bit name r/w default description 7-0 vendor_id1 r 19h vendor id 1. 8.1.6 vendor id register ? index 24h bit name r/w default description 7-0 vendor_id2 r 34h vendor id 2. 8.1.7 i2c address select register ? index 25h bit name r/w default description 7-1 i2c_addr r/w - the default value is determined by power on trap pin rts1#. the default i2c address is 0x5c and 0x5a for pull-up and pull-down respective. by writing 0x07, 0x04 and then new i2c_addr, programmer could change the default i2c address. write the same va lue again will disable the programmed i2c_addr and return to the default address. caution: during the enable sequence, the en_ara_mode will be also changed. user should program the correct value of en_ara_mode after changing i2c_addr.
F81865 may, 2010 v0.28p 77 0 en_ara_mode r/w 0 0: disable i2c ara. 1: enable i2c ara. 8.1.8 clock select register ? index 26h bit name r/w default description 7 clk24m_sel r/w 0 0: the clkin is 48mhz. 1: the clkin is 24mhz. 6-5 reserved - - reserved. 4 spi_tm_rst_sel r/w 0 spi time out status reset source select: 0: reset by inte rnal vdd3vok. 1: reset by internal vsbok. this bit is powered by vbat. 3-1 reserved - - reserved. 0 ur_gp_prog_en r/w 0 this bit is used to select the index 2ah. 0: index 2ah is the led mode select register. 1: index 2ah is the full ur5 ur6 select register. 8.1.9 rom address select register ? index 27h bit name r/w default description 7 rom_wr_en r/w 0 0: disable the memory write cycle, t he memory write cycle will be ignored. 1: enable the memory write cycle. 6 spi_en r/w - spi enable: 0: the spi is disabled. 1: the spi is enabled. the default value is determined by the power on trap pin sout2. pull down this pin to enable spi. this bit is powered by vsb3v. 5 fwh_en r/w - fwh enable: 0: the fwh is disabled. 1: the fwh is enabled. the default value is determined by the power on trap pin dtr2#. pull up this pin to enable fwh. accompany with spi_en. bios system as below list: fwh_en spi_en description 1 x this architecture uses fwh as primary bios 0 1 this architecture doesn?t implement fwh and uses spi as primary bios. 4 port_4e_en r/w - 0: the configuration register port is 2e/2f. 1: the configuration register port is 4e/4f. this register is power on trapped by sout1. pull down to select port 2e/2f.
F81865 may, 2010 v0.28p 78 3 seg_000e_en r/w - memory address 0x000e_0000 to 0x000e_ffff decode enable. 0: disable this range. 1: enable this range. the default value is determined by power on trap pin sout2. pull down to enable this bit. 2 seg_fff8_en r/w - memory address 0xfff8_0000 to 0xffff_ffff and 0x000f_0000 to 0x000f_ffff decode enable. 0: disable these ranges. 1: enable these ranges. the default value is determined by power on trap pin sout2. pull down to enable this bit. 1 seg_ffef_en r/w - memory address 0xffee_0000 to 0xffef_ffff decode enable. 0: disable this range. 1: enable this range. the default value is determined by power on trap pin sout2. pull down to enable this bit. 0 seg_fff0_en r/w 0 memory address 0xfff0_0000 to 0xfff7_ffff decode enable. 0: disable this range. 1: enable this range. 8.1.10 gpio4 enable register ? index 28h bit name r/w default description 7 gpio47_sel r/w 0 0: the function of sin4/gpio47 is sin4. 1: the function of sin4/gpio47 is gpio47. 6 gpio46_sel r/w 0 0: the function of so ut4/gpio46 is sout4. 1: the function of so ut4/gpio47 is gpio46. 5 gpio45_sel r/w 0 0: the function of ds r4#/gpio45 is dsr4#. 1: the function of ds r4#/gpio45 is gpio45. 4 gpio44_sel r/w 0 0: the function of rt s4#/gpio44 is rts4#. 1: the function of rt s4#/gpio44 is gpio44. 3 gpio43_sel r/w 0 0: the function of dt r4#/gpio43 is dtr4#. 1: the function of dt r4#/gpio43 is gpio43. 2 gpio42_sel r/w 0 0: the function of ct s4#/gpio42 is cts4#. 1: the function of ct s4#/gpio42 is gpio42. 1 gpio41_sel r/w 0 0: the function of ri4#/gpio41 is ri4#. 1: the function of ri 4#/gpio41 is gpio41. 0 gpio40_sel r/w 0 0: the function of dcd4#/gpio40 is dcd4#. 1: the function of dcd4 #/gpio40 is gpio40. 8.1.11 gpio3 enable register ? index 29h bit name r/w default description 7 gpio37_sel r/w 0 0: the function of sin3/gpio37 is sin3. 1: the function of sin3/gpio37 is gpio37.
F81865 may, 2010 v0.28p 79 6 gpio36_sel r/w 0 0: the function of so ut3/gpio36 is sout3. 1: the function of so ut3/gpio37 is gpio36. 5 gpio35_sel r/w 0 0: the function of ds r3#/gpio35 is dsr3#. 1: the function of ds r3#/gpio35 is gpio35. 4 gpio34_sel r/w 0 0: the function of rt s3#/gpio34 is rts3#. 1: the function of rt s3#/gpio34 is gpio34. 3 gpio33_sel r/w 0 0: the function of dt r3#/gpio33 is dtr3#. 1: the function of dt r3#/gpio33 is gpio33. 2 gpio32_sel r/w 0 0: the function of ct s3#/gpio32 is cts3#. 1: the function of ct s3#/gpio32 is gpio32. 1 gpio31_sel r/w 0 0: the function of ri3#/gpio31 is ri3#. 1: the function of ri 3#/gpio31 is gpio31. 0 gpio30_sel r/w 0 0: the function of dcd3#/gpio30 is dcd3#. 1: the function of dcd3 #/gpio30 is gpio30. 8.1.12 led mode select register (ur_gp_prog_en = 0) ? index 2ah (powered by vsb3v) bit name r/w default description 7-6 vsbled_sel r/w 2?b00 vsbled function select. 00: vsbled drives low. 01: vsbled is tri-state. 10: vsbled drives a 0.5hz clock. 11: vsbled drives a 1hz clock. (clock output is inversed with vccled clock output). 5-4 vccled_sel r/w 2?b00 vccled function select. 00: vccled drives low. 01: vccled is tri-state. 10: vccled drives a 0.5hz clock. 11: vccled drives a 1hz clock. (clock output is inversed with vsbled clock output).
F81865 may, 2010 v0.28p 80 3 fdc_gp_en r/w 0 fdc_gp_en, ur6_full_en, ur5_full_en, ur6_alt_en, ir_alt_en and rts6_alt_en will determine the functions of pin 9 to pin 21. pin 17 to pin 21 fdc_gp_en ur5_full_en ur6_full_en function 0 0 0 fdc inputs x 1 x ur5 modem control 1 0 x gpio60 ~ gpio64 x 0 1 gpio60 ~ gpio64 pin 12 to pin 16 fdc_gp_en ur5_full_en ur6_full_en function 0 0 0 fdc outputs x x 1 ur6 modem control 1 x 0 gpio53 ~ gpio57 x 1 0 gpio53 ~ gpio57 pin 10 to pin 11 fdc_gp_en ur6_alt_en ir_alt_en function 0 0 0 fdc outputs* x 1 x sin6_2/sout6_2 x 0 1 irrx_2/irtx_2 1 0 0 gpio51 ~ gpio52 pin 9 fdc_gp_en rts6_alt_en function 0 0 fdc outputs* x 1 rts6_2# 1 0 gpio50 *when ur5_full_en or ur6_full_en is set to ?1?, the pin function will become gpios. 2 ur6_gp_en r/w 0 this bit accompanying with ir_gp_en will determine the function of gpio05/sout6/irtx and gpio06/sin6/irrx. ur6_gp_en ir_gp_en function 0 0 gpio05/gpio06 1 x sout6_1/sin6_1 0 1 irtx_1/irrx_1 1 ur5_gp_en r/w 0 ur5 enable. (this bit affects the pi n function only when gpio12_sel and gpio13_sel is ?0?). 0: the function of gpio12/scl/ sout5 and gpio13/sda/sin5 will be determined by gpio12_sel and gpio13_sel. 1: the function of gp io12/scl/sout5 and gpio13/ sda/sin5 will be sout5 and sin5 respectively if gpio12_sel and gpio13_sel is ?0?. 0 ir_gp_en r/w 0 see ur6_gp_en for detail. 8.1.13 full ur5 ur6 select register (ur_gp_prog_en = 1) ? index 2ah (powered by vsb3v) bit name r/w default description 7 reserved - - reserved.
F81865 may, 2010 v0.28p 81 6 rts6_2_alt_en r/w 0 0: set this bit ?1? will enable rts6_2# output from densel#/gpio50/rts6_2#. 5 ur6_alt_en r/w 0 0: pin 10, pin 11 will functi on as moa#/gpio51/irrx_2 and drva#/gpio52/irtx_2 respectively. 1: pin 10, pin 11 will function as sin6_2 and sout6_2 respectively. 4 ir_alt_en r/w 0 this bit only has effect if ur6_alt_en is ?0? 0: pin 10, pin 11 will function as moa#/gpio51 and drva#/gpio52 respectively. 1: pin 10, pin 11 will function as irrx_2 and irtx_2 respectively. i f ir_alt_en is set ?1?, the ir rece iver input is determined by irrx2_2. 3 ur6_full_en r/w 0 set this bit will disable fdc and change the following pins to ur6 modem control pins: wdata# ? dcd6# dir# ? ri6# step# ? cts6# hdsel# ? dtr6# wgate# ? dsr6# gpio07 ? rts6# see fdc_gp_en for other fdc pins? function. 2 rts6_en r/w 0 set this bit will enable rts6# function. 0: gpio07/rts6# functions as gpio07 1: gpio07/rts6# functions as rts6#. 1 ur5_full_en r/w 0 set this bit will disable fdc and change the following pins to ur5 modem control pins: rdata# ? dcd5# trk0# ? ri5# index# ? cts5# wpt# ? dtr5# dskchg# ? dsr5# gpio14 ? rts5# see fdc_gp_en for other fdc pins? function. 0 rts5_en r/w 0 set this bit will enable rts5# function. 0: gpio14/rts5# functions as gpio14 1: gpio14/rts5# functions as rts5#. 8.1.14 gpio1 enable register ? index 2bh (powered by vsb3v) bit name r/w default description 7 gpio17_sel r/w 0 0: the function of peci/gpio17 is peci. 1: the function of peci/gpio17 is gpio17. 6 gpio16_sel r/w 0 0: the function of beep/gpio16 is beep. 1: the function of beep/gpio17 is gpio16. 5 gpio15_sel r/w 0 0: the function of wdtr st#/gpio15 is wdtrst#. 1: the function of wdtr st#/gpio15 is gpio15. 4 gpio14_sel r/w 1 dummy register. 3 gpio13_sel r/w 1 0: the function of gpio 13/sda/sin4 is sda. 1: the function of gpio 13/sda/sin4 is gpio13.
F81865 may, 2010 v0.28p 82 2 gpio12_sel r/w 1 0: the function of gpio 12/scl/sout4 is scl. 1: the function of gpio 12/scl/sout4 is gpio12. 1 gpio11_sel r/w 1 0: the function of gpio11/vccled is vccled. 1: the function of gpio 11/vccled is gpio11. 0 gpio10_sel r/w 1 0: the function of gpio10/vsbled is vsbled. 1: the function of gpio 10/vsbled is gpio10. 8.1.15 gpio2 enable register ? index 2ch (powered by vsb3v) bit name r/w default description 7 gpio27_sel r/w 0 0: the function of rsmr st#/gpio27 is rsmrst#. 1: the function of rsmr st#/gpio27 is gpio27. 6 gpio26_sel r/w 0 0: the function of pw rok/gpio26 is pwrok. 1: the function of pwrok/gpio27 is gpio26. 5 gpio25_sel r/w 0 0: the function of pson#/gpio25 is pson#. 1: the function of pso n#/gpio25 is gpio25. 4 gpio24_sel r/w 0 0: the function of s 3_in#/gpio25 is s3_in#. 1: the function of s 3_in#/gpio25 is gpio25. 3 gpio23_sel r/w 0 0: the function of pwso ut#/gpio23 is pwsout#. 1: the function of pwso ut#/gpio23 is gpio23. 2 gpio22_sel r/w 0 0: the function of pw sin#/gpio22 is pwsin#. 1: the function of pwsin#/gpio22 is gpio22. 1 gpio21_sel r/w 0 0: the function of atxpg/gpio21 is atxpg. 1: the function of atxpg/gpio21 is gpio21. 0 gpio20_sel r/w 0 0: the function of alert#/gpio20 is alert#. 1: the function of alert#/gpio20 is gpio20. 8.1.16 wakeup control register ? index 2dh (powered by vbat) bit name r/w default description 7 reserved - - reserved 6-4 reserved - - reserved 3 wakeup_en r/w 1 0: disable kb/mouse wakeup function. 1: enable kb/mouse wakeup function.
F81865 may, 2010 v0.28p 83 2-1 key_sel r/w 00 select the keyboard wakeup key. accompany with key_sel_add, there are several key select as list key_sel_add key_sel wake key 0 00 ctrl + esc 0 01 ctrl + f1 0 10 ctrl + space 0 11 any key 1 00 windows wakeup key 1 01 windows power key 1 10 ctrl + alt + backspace 1 11 ctrl + alt + delete 0 mo_sel r/w 0 select the mouse wakeup key. 0: wakeup by mouse clicking. 1: wakeup by mouse clicking or movement. 8.2 fdc registers (cr00) fdc device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 fdc_en r/w 1 0: disable fdc. 1: enable fdc. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of fdc base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w f0h the lsb of fdc base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selfdcirq r/w 06h select the irq channel for fdc. dma channel select register ? index 74h bit name r/w default description 7-3 reserved - - reserved. 2-0 selfdcdma r/w 010 select the dma channel for fdc. fdd mode register ? index f0h bit name r/w default description 7-5 reserved - - reserved. 4 fdc_sw_wp r/w 0 fdc software write protect. 0: write protect is determined by wpt# pin. 1: enable write protect.
F81865 may, 2010 v0.28p 84 3-2 if_mode r/w 11 00: model 30 mode. 01: ps/2 mode. 10: reserved. 11: at mode (default). 1 fdmamode r/w 1 0: enable burst mode. 1: non-busrt mode (default). 0 reserved r/w 0 reserved.(fintek test mode) fdd drive type register ? index f2h bit name r/w default description 7-2 reserved - - reserved. 1-0 fdd_type r/w 11 fdd drive type. fdd selection register ? index f4h bit name r/w default description 7-5 reserved - - reserved. 4-3 fdd_drt r/w 00 data rate table select, refer to table a. 00: select regular drives and 2.88 format. 01: reserved. 10: 2 mega tape. 11: reserved. 2 reserved - - reserved. 1-0 fdd_dt r/w 00 drive type select, refer to table b. table a data rate table select data rate selected data rate densel fdd_drt[1] fdd_drt[0] datarate1 datarate0 mfm fm 0 0 500k 250k 1 0 1 300k 150k 0 1 0 250k 125k 0 0 0 1 1 1meg --- 1 0 0 500k 250k 1 0 1 500k 250k 0 1 0 250k 125k 0 0 1 1 1 1meg --- 1 0 0 500k 250k 1 0 1 2meg --- 0 1 0 250k 125k 0 1 0 1 1 1meg --- 1
F81865 may, 2010 v0.28p 85 table b drive type fdd_dt1 fdd_dt0 drvden0 remark 0 0 densel 4/2/1 mb 3.5? 2/1 mb 5.25? 1/1.6/1 mb 3.5? (3-mode ) 0 1 datarate1 1 0 densel# 1 1 datarate0 8.3 parallel port registers (cr03) parallel port device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 prt_en r/w 1 0: disable parallel port. 1: enable parallel port. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of parallel port base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 78h the lsb of parallel port base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selprtirq r/w 7h select the irq channel for parallel port. dma channel select register ? index 74h bit name r/w default description 7-5 reserved - - reserved. 4 ecp_dma_mode r/w 0 0: non-burst mode dma. 1: enable burst mode dma. 3 reserved - - reserved. 2-0 selprtdma r/w 011 select the dma channel for parallel port. prt mode select register ? index f0h bit name r/w default description 7 reserved - - reserved. 6-3 ecp_fifo_thr r/w 1000 ecp fifo threshold.
F81865 may, 2010 v0.28p 86 2-0 prt_mode r/w 010 000: standard and bi-direction (spp) mode. 001: epp 1.9 and spp mode. 010: ecp mode (default). 011: ecp and epp 1.9 mode. 100: printer mode. 101: epp 1.7 and spp mode. 110: reserved. 111: ecp and epp1.7 mode. 8.4 hardware monito r registers (cr04) hardware monitor device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 hm_en r/w 1 0: disable hardware monitor. 1: enable hardware monitor. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 02h the msb of hardware monitor base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 95h the lsb of hardware monitor base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selhmirq r/w 0000 select the irq channel for hardware monitor. 8.5 kbc registers (cr05) kbc device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 kbc_en r/w 1 0: disable kbc. 1: enable kbc. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of kbc command port address. the address of data port is command port address + 4 base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 60h the lsb of kbc command port address. the address of data port is command port address + 4. kb irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selkirq r/w 0h select the irq channel for keyboard interrupt.
F81865 may, 2010 v0.28p 87 mouse irq channel select register ? index 72h bit name r/w default description 7-4 reserved - - reserved. 3-0 selmirq r/w 0h select the irq channel for ps/2 mouse interrupt. ps/2 swap register ? index feh (powered by vbat) bit name r/w default description 7 auto_det_en r/w 0 ps/2 auto detect enable. 0: disable auto detect. 1: enable auto detect, kb_mo_swap will be updated by hardware after lreset# de-assert. 6-5 reserved - - reserved 4 kb_mo_swap r/w 0 keyboard mouse swap. 0: keyboard/mouse is not swapped. 1: keyboard/mouse is swapped. this bit could be programmed by user. if auto_det_en is set, this bit is also updated by hardware. 3-0 kbc_test_bit r/w 1h fintek test mode bits. 8.6 gpio registers (cr06) *index port = base address + 5 gpio device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 gpio_en r/w 0 0: disable gpio i/o port. 1: enable gpio i/o port. base address high register ? index 60h bit name r/w default description 7-0 gp_base_addr_hi r/w 00h the msb of gpio i/o port address. base address low register ? index 61h bit name r/w default description 7-0 gp_base_addr_l o r/w 60h the lsb of gpio i/o port address. gpirq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selgpirq r/w 0h select the irq channel for gpio interrupt.
F81865 may, 2010 v0.28p 88 gpio0 output enable register ? index f0h bit name r/w default description 7 gpio07_oe r/w 0 0: gpio07 is input. 1: gpio07 is output. 6 gpio06_oe r/w 0 0: gpio06 is input. 1: gpio06 is output. 5 gpio05_oe r/w 0 0: gpio05 is input. 1: gpio05 is output. 4 gpio04_oe r/w 0 0: gpio04 is input. 1: gpio04 is output. 3 gpio03_oe r/w 0 0: gpio03 is input. 1: gpio03 is output. 2 gpio02_oe r/w 0 0: gpio02 is input. 1: gpio02 is output. 1 gpio01_oe r/w 0 0: gpio01 is input. 1: gpio01 is output. 0 gpio00_oe r/w 0 0: gpio00 is input. 1: gpio00 is output. gpio0 output data register ? index f1h bit name r/w default description 7 gpio07_data r/w 0 gpio07 out put data in output mode. 6 gpio06_data r/w 0 gpio06 out put data in output mode. 5 gpio05_data r/w 0 gpio05 out put data in output mode. 4 gpio04_data r/w 0 gpio04 out put data in output mode. 3 gpio03_data r/w 0 gpio03 out put data in output mode. 2 gpio02_data r/w 0 gpio02 out put data in output mode. 1 gpio01_data r/w 0 gpio01 out put data in output mode. 0 gpio00_data r/w 0 gpio00 out put data in output mode. gpio0 pin status register ? index f2h bit name r/w default description 7 gpio07_st r 1 gpio07 pin status. 6 gpio06_st r 1 gpio06 pin status. 5 gpio05_st r 1 gpio05 pin status. 4 gpio04_st r 1 gpio04 pin status. 3 gpio03_st r 1 gpio03 pin status. 2 gpio02_st r 1 gpio02 pin status. 1 gpio01_st r 1 gpio01 pin status. 0 gpio00_st r 1 gpio00 pin status.
F81865 may, 2010 v0.28p 89 gpio0 drive enable register ? index f3h bit name r/w default description 7 gpio07_drv_en r/w 0 gpio07 drive enable. 0: gpio07 is open drain. 1: gpio07 is push pull. 6 gpio06_drv_en r/w 0 gpio06 drive enable. 0: gpio06 is open drain. 1: gpio06 is push pull. 5 gpio05_drv_en r/w 0 gpio05 drive enable. 0: gpio05 is open drain. 1: gpio05 is push pull. 4 gpio04_drv_en r/w 0 gpio04 drive enable. 0: gpio04 is open drain. 1: gpio04 is push pull. 3 gpio03_drv_en r/w 0 gpio03 drive enable. 0: gpio03 is open drain. 1: gpio03 is push pull. 2 gpio02_drv_en r/w 0 gpio02 drive enable. 0: gpio02 is open drain. 1: gpio02 is push pull. 1 gpio01_drv_en r/w 0 gpio01 drive enable. 0: gpio01 is open drain. 1: gpio01 is push pull. 0 gpio00_drv_en r/w 0 gpio00 drive enable. 0: gpio00 is open drain. 1: gpio00 is push pull. gpio0 output mode 1 register ? index f4h bit name r/w default description 7-6 gpio03_mode r/w 00b gpio03 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio03_pw_sel. 5-4 gpio02_mode r/w 00b gpio02 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio02_pw_sel. 3-2 gpio01_mode r/w 00b gpio01 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio01_pw_sel.
F81865 may, 2010 v0.28p 90 1-0 gpio00_mode r/w 00b gpio00 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio00_pw_sel. gpio0 output mode 2 register ? index f5h bit name r/w default description 7-6 gpio07_mode r/w 00b gpio07 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio07_pw_sel. 5-4 gpio06_mode r/w 00b gpio06 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio06_pw_sel. 3-2 gpio05_mode r/w 00b gpio05 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio05_pw_sel. 1-0 gpio04_mode r/w 00b gpio04 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio04_pw_sel. gpio0 pulse width select 1 register ? index f6h bit name r/w default description 7-6 gpio03_pw_sel r/w 00b gpio03 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. 5-4 gpio02_pw_sel r/w 00b gpio02 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms.
F81865 may, 2010 v0.28p 91 3-2 gpio01_pw_sel r/w 00b gpio01 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. 1-0 gpio00_pw_sel r/w 00b gpio00 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. gpio0 pulse width select 2 register ? index f7h bit name r/w default description 7-6 gpio07_pw_sel r/w 00b gpio07 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. 5-4 gpio06_pw_sel r/w 00b gpio06 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. 3-2 gpio05_pw_sel r/w 00b gpio05 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. 1-0 gpio04_pw_sel r/w 00b gpio04 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. gpio0 interrupt enable register ? index f8h bit name r/w default description 7 gpio07_int_en r/w 0b 0: disable gpio07 interrupt 1: enable gpio07 interrupt when gpio07_int_st is set. 6 gpio06_int_en r/w 0b 0: disable gpio06 interrupt 1: enable gpio06 interrupt when gpio06_int_st is set. 5 gpio05_int_en r/w 0b 0: disable gpio05 interrupt 1: enable gpio05 interrupt when gpio05_int_st is set. 4 gpio04_int_en r/w 0b 0: disable gpio04 interrupt 1: enable gpio04 interrupt when gpio04_int_st is set. 3 gpio03_int_en r/w 0b 0: disable gpio03 interrupt 1: enable gpio03 interrupt when gpio03_int_st is set.
F81865 may, 2010 v0.28p 92 2 gpio02_int_en r/w 0b 0: disable gpio02 interrupt 1: enable gpio02 interrupt when gpio02_int_st is set. 1 gpio01_int_en r/w 0b 0: disable gpio01 interrupt 1: enable gpio01 interrupt when gpio01_int_st is set. 0 gpio00_int_en r/w 0b 0: disable gpio00 interrupt 1: enable gpio00 interrupt when gpio00_int_st is set. gpio0 interrupt status register ? index f9h bit name r/w default description 7 gpio07_int_st r/w 0b this bit only works when gpio07 is in input mode. 0: no change at gpio07 input. 1: change had occurred at gpio07 input. write ?1? to this bit to clear. 6 gpio06_int_st r/w 0b this bit only works when gpio06 is in input mode. 0: no change at gpio06 input. 1: change had occurred at gpio06 input. write ?1? to this bit to clear. 5 gpio05_int_st r/w 0b this bit only works when gpio05 is in input mode. 0: no change at gpio05 input. 1: change had occurred at gpio05 input. write ?1? to this bit to clear. 4 gpio04_int_st r/w 0b this bit only works when gpio04 is in input mode. 0: no change at gpio04 input. 1: change had occurred at gpio04 input. write ?1? to this bit to clear. 3 gpio03_int_st r/w 0b this bit only works when gpio03 is in input mode. 0: no change at gpio03 input. 1: change had occurred at gpio03 input. write ?1? to this bit to clear. 2 gpio02_int_st r/w 0b this bit only works when gpio02 is in input mode. 0: no change at gpio02 input. 1: change had occurred at gpio02 input. write ?1? to this bit to clear. 1 gpio01_int_st r/w 0b this bit only works when gpio01 is in input mode. 0: no change at gpio01 input. 1: change had occurred at gpio01 input. write ?1? to this bit to clear. 0 gpio00_int_st r/w 0b this bit only works when gpio00 is in input mode. 0: no change at gpio00 input. 1: change had occurred at gpio00 input. write ?1? to this bit to clear. gpio1 output enable register ? index e0h bit name r/w default description 7 gpio17_oe r/w 0 0: gpio17 is in input mode. 1: gpio17 is in output mode.
F81865 may, 2010 v0.28p 93 6 gpio16_oe r/w 0 0: gpio16 is in input mode. 1: gpio16 is in output mode. 5 gpio15_oe r/w 0 0: gpio15 is in input mode. 1: gpio15 is in output mode. 4 gpio14_oe r/w 0 0: gpio14 is in input mode. 1: gpio14 is in output mode. 3 gpio13_oe r/w 0 0: gpio13 is in input mode. 1: gpio13 is in output mode. 2 gpio12_oe r/w 0 0: gpio12 is in input mode. 1: gpio12 is in output mode. 1 gpio11_oe r/w 0 0: gpio11 is in input mode. 1: gpio11 is in output mode. 0 gpio10_oe r/w 0 0: gpio10 is in input mode. 1: gpio10 is in output mode. gpio1 output data register ? index e1h bit name r/w default description 7 gpio17_val r/w 1 0: gpio17 outputs 0 when in output mode. 1: gpio17 outputs1 when in output mode. 6 gpio16_val r/w 1 0: gpio16 outputs 0 when in output mode. 1: gpio16 outputs1 when in output mode. 5 gpio15_val r/w 1 0: gpio15 outputs 0 when in output mode. 1: gpio15 outputs 1 when in output mode. 4 gpio14_val r/w 1 0: gpio14 outputs 0 when in output mode. 1: gpio14 outputs 1 when in output mode. 3 gpio13_val r/w 1 0: gpio13 outputs 0 when in output mode. 1: gpio13 outputs 1 when in output mode. 2 gpio12_val r/w 1 0: gpio12 outputs 0 when in output mode. 1: gpio12 outputs 1 when in output mode. 1 gpio11_val r/w 1 0: gpio11 outputs 0 when in output mode. 1: gpio11 outputs 1 when in output mode. 0 gpio10_val r/w 1 0: gpio10 outputs 0 when in output mode. 1: gpio10 outputs 1 when in output mode. gpio1 pin status register ? index e2h bit name r/w default description 7 gpio17_in r - the pin status of gpio17. 6 gpio16_in r - the pin status of gpio16. 5 gpio15_in r - the pin status of gpio15. 4 gpio14_in r - the pin status of gpio14. 3 gpio13_in r - the pin status of gpio13. 2 gpio12_in r - the pin status of gpio12. 1 gpio11_in r - the pin status of gpio11. 0 gpio10_in r - the pin status of gpio10.
F81865 may, 2010 v0.28p 94 gpio1 drive enable register ? index e3h bit name r/w default description 7 gpio17_drv_en r/w 0 0: gpio17 is open drain in output mode. 1: gpio17 is push pull in output mode. 6 gpio16_drv_en r/w 0 0: gpio16 is open drain in output mode. 1: gpio16 is push pull in output mode. 5 gpio15_drv_en r/w 0 0: gpio15 is open drain in output mode. 1: gpio15 is push pull in output mode. 4 gpio14_drv_en r/w 0 0: gpio14 is open drain in output mode. 1: gpio14 is push pull in output mode. 3 gpio13_drv_en r/w 0 0: gpio13 is open drain in output mode. 1: gpio13 is push pull in output mode. 2 gpio12_drv_en r/w 0 0: gpio12 is open drain in output mode. 1: gpio12 is push pull in output mode. 1 gpio11_drv_en r/w 0 0: gpio11 is open drain in output mode. 1: gpio11 is push pull in output mode. 0 gpio10_drv_en r/w 0 0: gpio10 is open drain in output mode. 1: gpio10 is push pull in output mode. led s3 mode register ? index efh bit name r/w default description 7 led_s3_mode_en r/w 0 0: vsbled_s3_mode & vccled _s3_mode are disabled. 1: vsbled_s3_mode & vccled _s3_mode are enabled. 6-4 reserved - - reserved. 3-2 vsbled_s3_mode r/w 2?b00 vsbled mode in s3 state. 00: vsbled drives low. 01: vsbled is tri-state. 10: vsbled drives a 0.5hz clock. 11: vsbled drives a 1hz clock. (clock output is inversed with vccled clock output). 1-0 vccled_s3_mode r/w 2?b00 vccled mode in s3 state. 00: vccled drives low. 01: vccled is tri-state. 10: vccled drives a 0.5hz clock. 11: vccled drives a 1hz clock. (clock output is inversed with vsbled clock output). gpio2 output enable register ? index d0h bit name r/w default description 7 gpio27_oe r/w 0 0: gpio27 is in input mode. 1: gpio27 is in output mode. 6 gpio26_oe r/w 0 0: gpio26 is in input mode. 1: gpio26 is in output mode. 5 gpio25_oe r/w 0 0: gpio25 is in input mode. 1: gpio25 is in output mode.
F81865 may, 2010 v0.28p 95 4 gpio24_oe r/w 0 0: gpio24 is in input mode. 1: gpio24 is in output mode. 3 gpio23_oe r/w 0 0: gpio23 is in input mode. 1: gpio23 is in output mode. 2 gpio22_oe r/w 0 0: gpio22 is in input mode. 1: gpio22 is in output mode. 1 gpio21_oe r/w 0 0: gpio21 is in input mode. 1: gpio21 is in output mode. 0 gpio20_oe r/w 0 0: gpio20 is in input mode. 1: gpio20 is in output mode. gpio2 output data register ? index d1h bit name r/w default description 7 gpio27_val r/w 1 0: gpio27 outputs 0 when in output mode. 1: gpio27 outputs1 when in output mode. 6 gpio26_val r/w 1 0: gpio26 outputs 0 when in output mode. 1: gpio26 outputs1 when in output mode. 5 gpio25_val r/w 1 0: gpio25 outputs 0 when in output mode. 1: gpio25 outputs 1 when in output mode. 4 gpio24_val r/w 1 0: gpio24 outputs 0 when in output mode. 1: gpio24 outputs 1 when in output mode. 3 gpio23_val r/w 1 0: gpio23 outputs 0 when in output mode. 1: gpio23 outputs 1 when in output mode. 2 gpio22_val r/w 1 0: gpio22 outputs 0 when in output mode. 1: gpio22 outputs 1 when in output mode. 1 gpio21_val r/w 1 0: gpio21 outputs 0 when in output mode. 1: gpio21 outputs 1 when in output mode. 0 gpio20_val r/w 1 0: gpio20 outputs 0 when in output mode. 1: gpio20 outputs 1 when in output mode. gpio2 pin status register ? index d2h bit name r/w default description 7 gpio27_in r - the pin stat us of rsmrst#/gpio27. 6 gpio26_in r - the pin st atus of pwok/gpio26. 5 gpio25_in r - the pin status of ps_on#/gpio25. 4 gpio24_in r - the pin st atus of s3#/gpio24. 3 gpio23_in r - the pin stat us of pwsout#/gpio23. 2 gpio22_in r - the pin st atus of pwsin#/gpio22. 1 gpio21_in r - the pin stat us of atxpg_in#/gpio21. 0 gpio20_in r - the pin st atus of alert#/gpio20. gpio2 drive enable register ? index d3h bit name r/w default description 7 gpio27_drv_en r/w 0 0: gpio27 is open drain in output mode. 1: gpio27 is push pull in output mode.
F81865 may, 2010 v0.28p 96 6 gpio26_drv_en r/w 0 0: gpio26 is open drain in output mode. 1: gpio26 is push pull in output mode. 5 gpio25_drv_en r/w 0 0: gpio25 is open drain in output mode. 1: gpio25 is push pull in output mode. 4 gpio24_drv_en r/w 0 0: gpio24 is open drain in output mode. 1: gpio24 is push pull in output mode. 3 gpio23_drv_en r/w 0 0: gpio23 is open drain in output mode. 1: gpio23 is push pull in output mode. 2 gpio22_drv_en r/w 0 0: gpio22 is open drain in output mode. 1: gpio22 is push pull in output mode. 1 gpio21_drv_en r/w 0 0: gpio21 is open drain in output mode. 1: gpio21 is push pull in output mode. 0 gpio20_drv_en r/w 0 0: gpio20 is open drain in output mode. 1: gpio20 is push pull in output mode. gpio3 output enable register ? index c0h bit name r/w default description 7 gpio37_oe r/w 0 0: gpio37 is input. 1: gpio37 is output. 6 gpio36_oe r/w 0 0: gpio36 is input. 1: gpio36 is output. 5 gpio35_oe r/w 0 0: gpio35 is input. 1: gpio35 is output. 4 gpio34_oe r/w 0 0: gpio34 is input. 1: gpio34 is output. 3 gpio33_oe r/w 0 0: gpio33 is input. 1: gpio33 is output. 2 gpio32_oe r/w 0 0: gpio32 is input. 1: gpio32 is output. 1 gpio31_oe r/w 0 0: gpio31 is input. 1: gpio31 is output. 0 gpio30_oe r/w 0 0: gpio30 is input. 1: gpio30 is output. gpio3 output data register ? index c1h bit name r/w default description 7 gpio37_data r/w 1 gpio37 out put data in output mode. 6 gpio36_data r/w 1 gpio36 out put data in output mode. 5 gpio35_data r/w 1 gpio35 out put data in output mode. 4 gpio34_data r/w 1 gpio34 out put data in output mode. 3 gpio33_data r/w 1 gpio33 out put data in output mode. 2 gpio32_data r/w 1 gpio32 out put data in output mode. 1 gpio31_data r/w 1 gpio31 out put data in output mode. 0 gpio30_data r/w 1 gpio30 out put data in output mode.
F81865 may, 2010 v0.28p 97 gpio3 pin status register ? index c2h bit name r/w default description 7 gpio37_st r 1 gpio37 pin status. 6 gpio36_st r 1 gpio36 pin status. 5 gpio35_st r 1 gpio35 pin status. 4 gpio34_st r 1 gpio34 pin status. 3 gpio33_st r 1 gpio33 pin status. 2 gpio32_st r 1 gpio32 pin status. 1 gpio31_st r 1 gpio31 pin status. 0 gpio30_st r 1 gpio30 pin status. gpio3 drive enable register ? index c3h bit name r/w default description 7 gpio37_drv_en r/w 0 gpio37 drive enable. 0: gpio37 is open drain. 1: gpio37 is push pull. 6 gpio36_drv_en r/w 0 gpio36 drive enable. 0: gpio36 is open drain. 1: gpio36 is push pull. 5 gpio35_drv_en r/w 0 gpio35 drive enable. 0: gpio35 is open drain. 1: gpio35 is push pull. 4 gpio34_drv_en r/w 0 gpio34 drive enable. 0: gpio34 is open drain. 1: gpio34 is push pull. 3 gpio33_drv_en r/w 0 gpio33 drive enable. 0: gpio33 is open drain. 1: gpio33 is push pull. 2 gpio32_drv_en r/w 0 gpio32 drive enable. 0: gpio32 is open drain. 1: gpio32 is push pull. 1 gpio31_drv_en r/w 0 gpio31 drive enable. 0: gpio31 is open drain. 1: gpio31 is push pull. 0 gpio30_drv_en r/w 0 gpio30 drive enable. 0: gpio30 is open drain. 1: gpio30 is push pull. gpio4 output enable register ? index b0h bit name r/w default description 7 gpio47_oe r/w 0 0: gpio47 is input. 1: gpio47 is output. 6 gpio46_oe r/w 0 0: gpio46 is input. 1: gpio46 is output. 5 gpio45_oe r/w 0 0: gpio45 is input. 1: gpio45 is output.
F81865 may, 2010 v0.28p 98 4 gpio44_oe r/w 0 0: gpio44 is input. 1: gpio44 is output. 3 gpio43_oe r/w 0 0: gpio43 is input. 1: gpio43 is output. 2 gpio42_oe r/w 0 0: gpio42 is input. 1: gpio42 is output. 1 gpio41_oe r/w 0 0: gpio41 is input. 1: gpio41 is output. 0 gpio40_oe r/w 0 0: gpio40 is input. 1: gpio40 is output. gpio4 output data register ? index b1h bit name r/w default description 7 gpio47_data r/w 1 gpio47 out put data in output mode. 6 gpio46_data r/w 1 gpio46 out put data in output mode. 5 gpio45_data r/w 1 gpio45 out put data in output mode. 4 gpio44_data r/w 1 gpio44 out put data in output mode. 3 gpio43_data r/w 1 gpio43 out put data in output mode. 2 gpio42_data r/w 1 gpio42 out put data in output mode. 1 gpio41_data r/w 1 gpio41 out put data in output mode. 0 gpio40_data r/w 1 gpio40 out put data in output mode. gpio4 pin status register ? index b2h bit name r/w default description 7 gpio47_st r 1 gpio47 pin status. 6 gpio46_st r 1 gpio46 pin status. 5 gpio45_st r 1 gpio45 pin status. 4 gpio44_st r 1 gpio44 pin status. 3 gpio43_st r 1 gpio43 pin status. 2 gpio42_st r 1 gpio42 pin status. 1 gpio41_st r 1 gpio41 pin status. 0 gpio40_st r 1 gpio40 pin status. gpio4 drive enable register ? index b3h bit name r/w default description 7 gpio47_drv_en r/w 0 gpio47 drive enable. 0: gpio47 is open drain. 1: gpio47 is push pull. 6 gpio46_drv_en r/w 0 gpio46 drive enable. 0: gpio46 is open drain. 1: gpio46 is push pull. 5 gpio45_drv_en r/w 0 gpio45 drive enable. 0: gpio45 is open drain. 1: gpio45 is push pull.
F81865 may, 2010 v0.28p 99 4 gpio44_drv_en r/w 0 gpio44 drive enable. 0: gpio44 is open drain. 1: gpio44 is push pull. 3 gpio43_drv_en r/w 0 gpio43 drive enable. 0: gpio43 is open drain. 1: gpio43 is push pull. 2 gpio42_drv_en r/w 0 gpio42 drive enable. 0: gpio42 is open drain. 1: gpio42 is push pull. 1 gpio41_drv_en r/w 0 gpio41 drive enable. 0: gpio41 is open drain. 1: gpio41 is push pull. 0 gpio40_drv_en r/w 0 gpio40 drive enable. 0: gpio40 is open drain. 1: gpio40 is push pull. gpio5 output enable register ? index a0h bit name r/w default description 7 gpio57_oe r/w 0 0: gpio57 is input. 1: gpio57 is output. 6 gpio56_oe r/w 0 0: gpio56 is input. 1: gpio56 is output. 5 gpio55_oe r/w 0 0: gpio55 is input. 1: gpio55 is output. 4 gpio54_oe r/w 0 0: gpio54 is input. 1: gpio54 is output. 3 gpio53_oe r/w 0 0: gpio53 is input. 1: gpio53 is output. 2 gpio52_oe r/w 0 0: gpio52 is input. 1: gpio52 is output. 1 gpio51_oe r/w 0 0: gpio51 is input. 1: gpio51 is output. 0 gpio50_oe r/w 0 0: gpio50 is input. 1: gpio50 is output. gpio5 output data register ? index a1h bit name r/w default description 7 gpio57_data r/w 1 gpio57 out put data in output mode. 6 gpio56_data r/w 1 gpio56 out put data in output mode. 5 gpio55_data r/w 1 gpio55 out put data in output mode. 4 gpio54_data r/w 1 gpio54 out put data in output mode. 3 gpio53_data r/w 1 gpio53 out put data in output mode. 2 gpio52_data r/w 1 gpio52 out put data in output mode. 1 gpio51_data r/w 1 gpio51 out put data in output mode. 0 gpio50_data r/w 1 gpio50 out put data in output mode.
F81865 may, 2010 v0.28p 100 gpio5 pin status register ? index a2h bit name r/w default description 7 gpio57_st r 1 gpio57 pin status. 6 gpio56_st r 1 gpio56 pin status. 5 gpio55_st r 1 gpio55 pin status. 4 gpio54_st r 1 gpio54 pin status. 3 gpio53_st r 1 gpio53 pin status. 2 gpio52_st r 1 gpio52 pin status. 1 gpio51_st r 1 gpio51 pin status. 0 gpio50_st r 1 gpio50 pin status. gpio5 drive enable register ? index a3h bit name r/w default description 7 gpio57_drv_en r/w 0 gpio57 drive enable. 0: gpio57 is open drain. 1: gpio57 is push pull. 6 gpio56_drv_en r/w 0 gpio56 drive enable. 0: gpio56 is open drain. 1: gpio56 is push pull. 5 gpio55_drv_en r/w 0 gpio55 drive enable. 0: gpio55 is open drain. 1: gpio55 is push pull. 4 gpio54_drv_en r/w 0 gpio54 drive enable. 0: gpio54 is open drain. 1: gpio54 is push pull. 3 gpio53_drv_en r/w 0 gpio53 drive enable. 0: gpio53 is open drain. 1: gpio53 is push pull. 2 gpio52_drv_en r/w 0 gpio52 drive enable. 0: gpio52 is open drain. 1: gpio52 is push pull. 1 gpio51_drv_en r/w 0 gpio51 drive enable. 0: gpio51 is open drain. 1: gpio51 is push pull. 0 gpio50_drv_en r/w 0 gpio50 drive enable. 0: gpio50 is open drain. 1: gpio50 is push pull. gpio6 output enable register ? index 90h bit name r/w default description 7-5 reserved - - reserved. 4 gpio64_oe r/w 0 0: gpio64 is input. 1: gpio64 is output. 3 gpio63_oe r/w 0 0: gpio63 is input. 1: gpio63 is output.
F81865 may, 2010 v0.28p 101 2 gpio62_oe r/w 0 0: gpio62 is input. 1: gpio62 is output. 1 gpio61_oe r/w 0 0: gpio61 is input. 1: gpio61 is output. 0 gpio60_oe r/w 0 0: gpio60 is input. 1: gpio60 is output. gpio6 output data register ? index 91h bit name r/w default description 7-5 reserved - - reserved. 4 gpio64_data r/w 1 gpio64 out put data in output mode. 3 gpio63_data r/w 1 gpio63 out put data in output mode. 2 gpio62_data r/w 1 gpio62 out put data in output mode. 1 gpio61_data r/w 1 gpio61 out put data in output mode. 0 gpio60_data r/w 1 gpio60 out put data in output mode. gpio6 pin status register ? index 92h bit name r/w default description 7-5 reserved - - reserved. 4 gpio64_st r 1 gpio64 pin status. 3 gpio63_st r 1 gpio63 pin status. 2 gpio62_st r 1 gpio62 pin status. 1 gpio61_st r 1 gpio61 pin status. 0 gpio60_st r 1 gpio60 pin status. gpio6 drive enable register ? index 93h bit name r/w default description 7-5 reserved - - reserved. 4 gpio64_drv_en r/w 0 gpio64 drive enable. 0: gpio64 is open drain. 1: gpio64 is push pull. 3 gpio63_drv_en r/w 0 gpio63 drive enable. 0: gpio63 is open drain. 1: gpio63 is push pull. 2 gpio62_drv_en r/w 0 gpio62 drive enable. 0: gpio62 is open drain. 1: gpio62 is push pull. 1 gpio61_drv_en r/w 0 gpio61 drive enable. 0: gpio61 is open drain. 1: gpio61 is push pull. 0 gpio60_drv_en r/w 0 gpio60 drive enable. 0: gpio60 is open drain. 1: gpio60 is push pull.
F81865 may, 2010 v0.28p 102 8.7 wdt registers (cr07) wdt device base address enable register ? index 30h bit name r/w default description 7-1 reserved - 0 reserved 0 wdt_en r/w 0 0: disable wdt base address. 1: enable wdt base address. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of wdt base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 00h the lsb of wdt base address. watchdog control configuration register 1 ? index f5h bit name r/w default description 7 reserved r 0 reserved 6 wdtmout_sts r/w 0 if watchdog timeout event occurs, this bit will be set to 1. write a 1 to this bit will clear it to 0. 5 wd_en r/w 0 if this bit is set to 1, the counting of watchdog time is enabled. 4 wd_pulse r/w 0 select output mode (0: level, 1: pulse) of rstout# by setting this bit. 3 wd_unit r/w 0 select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit. 2 wd_hactive r/w 0 select output polarity of rstout# (1: hi gh active, 0: low acti ve) by setting this bit. 1-0 wd_pswidth r/w 0 select output pulse width of rstout# 0: 1 ms 1: 25 ms 2: 125 ms 3: 5 sec watchdog timer configuration register 2 ? index f6h bit name r/w default description 7-0 wd_time r/w 0 time of watchdog timer (0~255) watchdog pme enable configuration register 2 ? index fah bit name r/w default description 7 wdt_pme r -- the pme status. this bit will set when wdt_pme_en is set and the watchdog timer is 1 unit before time out (or time out). 6 wdt_pme_en r/w 0 0: disable watchdog pme. 1: enable watchdog pme. 5-1 reserved -- -- reserved. 0 wdout_en r/w 0 0: disable watchdog time out output via wdtrst#. 1: enable watchdog time out output via wdtrst#. 8.8 spi registers (cr08) spi control register ? index f0h bit name r/w default description 7-6 reserved - - reserved. 5 sptie r/w 0 spi interrupt enable. set to 1, spie enabled, set to 0 spie disabled.
F81865 may, 2010 v0.28p 103 4 mstr r/w 1 master mode select. set to 1, spi functi on is master mode; set to 0 is disable spi function 3 cpol r/w 0 clock polarity this bit selects inverted or n on-inverted spi clock. set to 1, active low clock selected; sck idles high. set to 0, active high clock selected; sck idles low. 2 cpha r/w 0 clock phase. this bit is used to shift the sck serial clock. set to 1, the first sck edge is issued at the beginning of the transfer operation. set to 0, the first sck edge is issued one-half cycle into the transfer operation. 1 reserved - 0 reserved 0 lsbfe r/w 0 this bit control data shift from lsb or msb. set to 1, data is transferred from lsb to msb. set to 0, data is transferred from msb to lsb. reserved ? index f1h bit name r/w default description 7-0 reserved - - reserved spi baud rate divisor register ? index f2h bit name r/w default description 7-3 reserved - 1 reserved 2-0 baud_val r/w 1 this register decides to sck frequency. baud rate divisor equation is 2^ (baud_val + 1) spi status register ? index f3h bit name r/w default description 7 spie r/w 0 spi interrupt status. when spi is trans ferred or received data from device finish, this bit will be set. write 1 to clear this bit. 6-4 reserved r/w - reserved. 3 sptef r 0 spi operation status. when spi is transfe rred or received data from device, this bit will be set 1, clear by spi operation finish. 2-0 reserved - - reserved spi high byte data register ? index f4h bit name r/w default description 7-0 h_data r 0 when spi is received 16 bits data from device. this register saves high byte data. spi command data register ? index f5h bit name r/w default description 7-0 cmd_data r/w 0 this register provides command value for flash command. spi chip select register ? index f6h bit name r/w default description 7-2 reserved - - reserved 1 cs1 r/w 0 chip select 1. to select device 1 0 cs0 r/w 0 chip select 0. to select device 0 spi memory mapping register ? index f7h bit name r/w default description 7-3 reserved - 0 reserved
F81865 may, 2010 v0.28p 104 2-0 mem_map r/w - this register decides memory size. 3?b000: 512k bit. 3?b001: 1024k bit. 3?b100: 2048k bit. 3?b011: 4096k bit. 3?b100: 8092k bit. spi operate register ? index f8h bit name r/w default description 7 type r/w 0 this bit decide flash continuous programmi ng mode. set to 1, if programming continuous mode is same as the sst flas h. set to 0 if programming continuous mode is same as the atmel flash 6 io_spi r/w 0 this bit control spi function transfer 8 bit command to device. clear 0 by operation finish. 5 rdsr r/w 0 this bit control spi function read status from to device. clear 0 by operation finish. 4 wrsr r/w 0 this bit control spi function write status to device. clear 0 by operation finish. 3 sector_erase r/w 0 this bit control spi function se ctor erase device. clear 0 by operation finish. 2 read_id r/w 0 this bit control spi function re ad id from device. clear 0 by operation finish. 1 prog r/w 0 this bit control spi function program data to device or set to 1 when memory cycle for lpc interface program flash. clear 0 by operation finish. 0 read r/w 0 this bit control spi function read data from device or set to 1 when memory cycle for lpc interface read flash. clear 0 by operation finish. spi low byte data register ? index fah bit name r/w default description 7-0 l_data r 0 when spi is received 16 bits or 8 bits dat a from device. this register saves low byte data. spi address high byte register ? index fbh bit name r/w default description 7-0 addr_h_byte r/w 0 this register provides high byte ad dress for sector erase, program, read operation. spi address medium byte register ? index fch bit name r/w default description 7-0 addr_m_byte r/w 0 this register provides medium byte a ddress for sector erase, program, read operation. spi address low byte register ? index fdh bit name r/w default description 7-0 addr_l_byte r/w 0 this register provides low byte addr ess for sector erase, program, read operation. spi program byte register ? index feh bit name r/w default description 7-0 porg_byte r/w 0 this regist er provides number to program flash for continuous mode. spi write data register ? index ffh bit name r/w default description 7-0 wr_dat r/w 0 this register provides data to write flash for program, write status function.
F81865 may, 2010 v0.28p 105 8.9 pme and acpi registers (cr0a) device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 pme_en r/w 0 0: disable pme. 1: enable pme. pme event enable 1 register ? index f0h bit name r/w default description 7 reserved - - reserved 6 wdt_pme_en r/w 0 watchdog pme event enable. 0: disable watchdog pme event. 1: enable watchdog pme event. 5 gp_pme_en r/w 0 gpio pme event enable. 0: disable gpio pme event. 1: enable gpio pme event. 4 mo_pme_en r/w 0 mouse pme event enable. 0: disable mouse pme event. 1: enable mouse pme event. 3 kb_pme_en r/w 0 keyboard pme event enable. 0: disable keyboard pme event. 1: enable keyboard pme event. 2 hm_pme_en r/w 0 hardware monitor pme event enable. 0: disable hardware monitor pme event. 1: enable hardware monitor pme event. 1 prt_pme_en r/w 0 parallel port pme event enable. 0: disable parallel port pme event. 1: enable parallel port pme event. 0 fdc_pme_en r/w 0 fdc pme event enable. 0: disable fdc pme event. 1: enable fdc pme event. pme event enable 2 register ? index f1h bit name r/w default description 7-6 reserved - - reserved 5 ur6_pme_en r/w 0 uart 6 pme event enable. 0: disable uart 6 pme event. 1: enable uart 6 pme event. 4 ur5_pme_en r/w 0 uart 5 pme event enable. 0: disable uart 5 pme event. 1: enable uart 5 pme event. 3 ur4_pme_en r/w 0 uart 4 pme event enable. 0: disable uart 4 pme event. 1: enable uart 4 pme event. 2 ur3_pme_en r/w 0 uart 3 pme event enable. 0: disable uart 3 pme event. 1: enable uart 3 pme event.
F81865 may, 2010 v0.28p 106 1 ur2_pme_en r/w 0 uart 2 pme event enable. 0: disable uart 2 pme event. 1: enable uart 2 pme event. 0 ur1_pme_en r/w 0 uart 1 pme event enable. 0: disable uart 1 pme event. 1: enable uart 1 pme event. pme event status 1 register ? index f2h bit name r/w default description 7 reserved - - reserved 6 wdt_pme_st r/w - watchdog pme event status. 0: watchdog has no pme event. 1: watchdog has a pme event to assert. write 1 to clear to be ready for next pme event. 5 gp_pme_st r/w - gpio pme event status. 0: gpio has no pme event. 1: gpio has a pme event to assert. write 1 to clear to be ready for next pme event. 4 mo_pme_st r/w - mouse pme event status. 0: mouse has no pme event. 1: mouse has a pme event to assert. writ e 1 to clear to be ready for next pme event. 3 kb_pme_st r/w - keyboard pme event status. 0: keyboard has no pme event. 1: keyboard has a pme event to assert. write 1 to clear to be ready for next pme event. 2 hm_pme_st r/w - hardware monitor pme event status. 0: hardware monitor has no pme event. 1: hardware monitor has a pme event to assert. write 1 to clear to be ready for next pme event. 1 prt_pme_st r/w - parallel port pme event status. 0: parallel port has no pme event. 1: parallel port has a pme event to assert. write 1 to clear to be ready for next pme event. 0 fdc_pme_st r/w - fdc pme event status. 0: fdc has no pme event. 1: fdc has a pme event to assert. write 1 to clear to be ready for next pme event. pme event status 1 register ? index f3h bit name r/w default description 7-6 reserved - - reserved 5 ur6_pme_st r/w - uart 6 pme event status. 0: uart 6 has no pme event. 1: uart 6 has a pme event to assert. write 1 to clear to be ready for next pme event. 4 ur5_pme_st r/w - uart 5 pme event status. 0: uart 5 has no pme event. 1: uart 5 has a pme event to assert. write 1 to clear to be ready for next pme event.
F81865 may, 2010 v0.28p 107 3 ur4_pme_st r/w - uart 4 pme event status. 0: uart 4 has no pme event. 1: uart 4 has a pme event to assert. write 1 to clear to be ready for next pme event. 2 ur3_pme_st r/w - uart 3 pme event status. 0: uart 3 has no pme event. 1: uart 3 has a pme event to assert. write 1 to clear to be ready for next pme event. 1 ur2_pme_st r/w - uart 2 pme event status. 0: uart 2 has no pme event. 1: uart 2 has a pme event to assert. write 1 to clear to be ready for next pme event. 0 ur1_pme_st r/w - uart 1 pme event status. 0: uart 1 has no pme event. 1: uart 1 has a pme event to assert. write 1 to clear to be ready for next pme event. acpi control register ? index f4h bit name r/w default description 7 ts3 r/w 0 kbc s3 test mode register. (fintek only) set one to force kbc into s3 state. 6 spi_rst_en r/w 0 0: disable spi time out reset via pwrok. 1: enable spi time out reset via pwrok. 5 key_sel_add r/w 0 see key_sel for detail. 4 en_kbwakeup r/w 0 set one to enable key board wakeup event asserted via pwsout#. 3 en_mowakeup r/w 0 set one to enable mouse wakeup event asserted via pwsout#. 2-1 pwrctrl r/w 11 the acpi control the pson_n to the following stages 00 : keep last state 01 :bypass mode (always on without psout#) 10 : always on 11: always off 0 vsb_pwr_loss r/w 0 when vsb 3v comes, it will set to 1 (default). then write 1 to clear it. acpi control register ? index f5h bit name r/w default description 7 soft_rst_acpi r/w 0 software reset to acpi (auto clear after reset) 6-5 pwrok_delay r/w 00 pwrok additional delay. 00: 0ms 01: 100ms. 10: 200ms. 11: 400ms. 4-3 delay r/w 11 the pwrok delay timing from vdd3vok by followed setting 00 : 100ms 01 : 200ms 10 : 300ms 11 : 400ms 2 vindb_en r/w 1 enable the pc irstin_n and atxpwgd de-bounce. 1-0 reserved - - reserved
F81865 may, 2010 v0.28p 108 acpi control register ? index f6h bit name r/w default description 7 s3_sel r/w 0 0: the s3 state for kbc is controlled by vdd3vok. 1: the s3 state for kbc is force to 1 or inverted of s3# select by ts3. 6-5 reserved - - reserved. 4 pson_del_en r/w 0 pson# delay enable. 0: pson# is the invert of s3#. 1: pson# will delay 4 seconds to turn on after last turn off. 3-2 reserved - - reserved 1 bypass_db_acpi r/w 0 disable all the de-bounce circuit. 0 test_pwr_en r/w 0 for testing only. 8.10 rtc registers (cr0b) device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 rtc_en r/w 0 0: disable rtc i/o access. 1: enable rtc i/o access. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of rtc i/o port address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 60h the lsb of rtc i/o port address. kb irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selrtcirq r/w 0h select the irq channel for rtc interrupt. 8.11 uart1 registers (cr10) uart 1 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 ur1_en r/w 1 1: disable uart 1. 1: enable uart 1. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of uart 1 base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w f8h the lsb of uart 1 base address.
F81865 may, 2010 v0.28p 109 irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selur1irq r/w 4h select t he irq channel for uart 1. irq share register ? index f0h bit name r/w default description 7 ur1_9bit_mode r/w 0 0: normal uart function 1: enable 9-bit mode (multi-drop mode). in the 9-bit mode, the parity bit becomes the address/data bit. 6 ur1_auto_addr r/w 0 this bit works only in 9-bit mode. 0: the sm2 bit will be cleared by host, so that data could be received. 1: the sm2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by saddr_ur1 and saden_ur1) 5 ur1_rs485_inv r/w 0 invert rts# if ur1_rs485_en is set. 4 ur1_rs485_en r/w 0 0: rs232 driver. 1: rs485 driver. auto drive rts# high when transmitting data, otherwise is kept low . 3-2 reserved - - reserved. 1 ur1irq_mode r/w 0 0 : pci irq sharing mode. 1 : isa irq sharing mode. this bit is effective in irq sharing mode. 0 ur1irq_share r/w 0 0 : irq is not sharing with other device. 1 : irq is sharing with other device. clock register ? index f2h bit name r/w default description 7-2 reserved - - reserved. 1-0 ur1_clk_sel r/w 00b select the clock source for uart1. 00: 1.8432mhz. 01: 18.432mhz. 10: 24mhz. 11: 14.769mhz. 9bit-mode slave address register ? index f4h bit name r/w default description 7-0 saddr_ur1 r/w 00h this byte accompanying with saden_ur1 will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. follow the description to determine the given address and broadcast address: 1. given address: if bit n of saden_ur1 is ?0?, then the corresponding bit of saddr_ur1 is don?t care. 2. broadcast address: if bit n of ored saddr_ur1 and saden_ur1 is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr_ur1 0101_1100b saden_ur1 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b
F81865 may, 2010 v0.28p 110 9bit-mode slave address mask register ? index f5h bit name r/w default description 7:0 saden_ur1 r/w 00h this byte accompanying with saddr_ur1 will determine the given address and broadcast address in 9-bit mode. the uart_ur1 will response to both given and broadcast address. follow the description to determine the given address and broadcast address: 3. given address: if bit n of saden_ur1 is ?0?, then the corresponding bit of saddr_ur1 is don?t care. 4. broadcast address: if bit n of ored saddr_ur1 and saden_ur1 is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr_ur1 0101_1100b saden_ur1 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b 8.12 uart2 registers (cr11) uart 2 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 ur2_en r/w 1 0: disable uart 2 1: enable uart 2. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 02h the msb of uart 2 base address. base address low register ? index 61h bit name r/w default description 7-1 base_addr_lo r/w f8h the l sb of uart 2 base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selur12rq r/w 3h select the irq channel for uart 2. irq share register ? index f0h bit name r/w default description 7 ur2_9bit_mode r/w 0 0: normal uart function 1: enable 9-bit mode (multi-drop mode). in the 9-bit mode, the parity bit becomes the address/data bit. 6 ur2_auto_addr r/w 0 this bit works only in 9-bit mode. 0: the sm2 bit will be cleared by host, so that data could be received. 1: the sm2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by saddr_ur2 and saden_ur2) 5 ur2_rs485_inv r/w 0 invert rts# if ur2_rs485_en is set. 4 ur2_rs485_en r/w 0 0: rs232 driver. 1: rs485 driver. auto drive rts# high when transmitting data, otherwise is kept low .
F81865 may, 2010 v0.28p 111 3-2 reserved - - reserved. 1 ur2irq_mode r/w 0 0 : pci irq sharing mode. 1 : isa irq sharing mode. this bit is effective in irq sharing mode. 0 ur2irq_share r/w 0 0 : irq is not sharing with other device. 1 : irq is sharing with other device. clock register ? index f2h bit name r/w default description 7-2 reserved - - reserved. 1-0 ur2_clk_sel r/w 00b select the clock source for uart2. 00: 1.8432mhz. 01: 18.432mhz. 10: 24mhz. 11: 14.769mhz. 9bit-mode slave address register ? index f4h bit name r/w default description 7-0 saddr_ur2 r/w 00h this byte accompanying with saden_ur2 will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. follow the description to determine the given address and broadcast address: 5. given address: if bit n of saden_ur2 is ?0?, then the corresponding bit of saddr_ur2 is don?t care. 6. broadcast address: if bit n of ored saddr_ur2 and saden_ur2 is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr_ur2 0101_1100b saden_ur2 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b 9bit-mode slave address mask register ? index f5h bit name r/w default description 7:0 saden_ur2 r/w 00h this byte accompanying with saddr_ur2 will determine the given address and broadcast address in 9-bit mode. the uart_ur2 will response to both given and broadcast address. follow the description to determine the given address and broadcast address: 7. given address: if bit n of saden_ur2 is ?0?, then the corresponding bit of saddr_ur2 is don?t care. 8. broadcast address: if bit n of ored saddr_ur2 and saden_ur2 is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr_ur2 0101_1100b saden_ur2 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b
F81865 may, 2010 v0.28p 112 8.13 uart3 registers (cr12) uart 3 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 ur3_en r/w 1 0: disable uart 3. 1: enable uart 3. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of uart 3 base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w e8h the lsb of uart 3 base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selur3irq r/w 3h select t he irq channel for uart 3. irq share register ? index f0h bit name r/w default description 7 ur3_9bit_mode r/w 0 0: normal uart function 1: enable 9-bit mode (multi-drop mode). in the 9-bit mode, the parity bit becomes the address/data bit. 6 ur3_auto_addr r/w 0 this bit works only in 9-bit mode. 0: the sm2 bit will be cleared by host, so that data could be received. 1: the sm2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by saddr_ur3 and saden_ur3) 5 ur3_rs485_inv r/w 0 invert rts# if ur3_rs485_en is set. 4 ur3_rs485_en r/w 0 0: rs232 driver. 1: rs485 driver. auto drive rts# high when transmitting data, otherwise is kept low . 3-2 reserved - - reserved. 1 ur3irq_mode r/w 0 0 : pci irq sharing mode. 1 : isa irq sharing mode. this bit is effective in irq sharing mode. 0 ur3irq_share r/w 0 0 : irq is not sharing with other device. 1 : irq is sharing with other device. clock register ? index f2h bit name r/w default description 7-2 reserved - - reserved. 1-0 ur3_clk_sel r/w 00b select the clock source for uart3. 00: 1.8432mhz. 01: 18.432mhz. 10: 24mhz. 11: 14.769mhz.
F81865 may, 2010 v0.28p 113 9bit-mode slave address register ? index f4h bit name r/w default description 7-0 saddr_ur3 r/w 00h this byte accompanying with saden_ur3 will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. follow the description to determine the given address and broadcast address: 9. given address: if bit n of saden_ur3 is ?0?, then the corresponding bit of saddr_ur3 is don?t care. 10. broadcast address: if bit n of ored saddr_ur3 and saden_ur3 is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr_ur3 0101_1100b saden_ur3 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b 9bit-mode slave address mask register ? index f5h bit name r/w default description 7:0 saden_ur3 r/w 00h this byte accompanying with saddr_ur3 will determine the given address and broadcast address in 9-bit mode. the uart_ur3 will response to both given and broadcast address. follow the description to determine the given address and broadcast address: 11. given address: if bit n of saden_ur3 is ?0?, then the corresponding bit of saddr_ur3 is don?t care. 12. broadcast address: if bit n of ored saddr_ur3 and saden_ur3 is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr_ur3 0101_1100b saden_ur3 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b 8.14 uart4 registers (cr13) uart 4 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 ur3_en r/w 1 0: disable uart 4. 1: enable uart 4. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of uart 4 base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w e8h the lsb of uart 4 base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selur4irq r/w 3h select t he irq channel for uart 4.
F81865 may, 2010 v0.28p 114 irq share register ? index f0h bit name r/w default description 7 ur4_9bit_mode r/w 0 0: normal uart function 1: enable 9-bit mode (multi-drop mode). in the 9-bit mode, the parity bit becomes the address/data bit. 6 ur4_auto_addr r/w 0 this bit works only in 9-bit mode. 0: the sm2 bit will be cleared by host, so that data could be received. 1: the sm2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by saddr_ur4 and saden_ur4) 5 ur4_rs485_inv r/w 0 invert rts# if ur4_rs485_en is set. 4 ur4_rs485_en r/w 0 0: rs232 driver. 1: rs485 driver. auto drive rts# high when transmitting data, otherwise is kept low . 3-2 reserved - - reserved. 1 ur4irq_mode r/w 0 0 : pci irq sharing mode. 1 : isa irq sharing mode. this bit is effective in irq sharing mode. 0 ur4irq_share r/w 0 0 : irq is not sharing with other device. 1 : irq is sharing with other device. clock register ? index f2h bit name r/w default description 7-2 reserved - - reserved. 1-0 ur4_clk_sel r/w 00b select the clock source for uart4. 00: 1.8432mhz. 01: 18.432mhz. 10: 24mhz. 11: 14.769mhz. 9bit-mode slave address register ? index f4h bit name r/w default description 7-0 saddr_ur4 r/w 00h this byte accompanying with saden_ur4 will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. follow the description to determine the given address and broadcast address: 13. given address: if bit n of saden_ur4 is ?0?, then the corresponding bit of saddr_ur4 is don?t care. 14. broadcast address: if bit n of ored saddr_ur4 and saden_ur4 is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr_ur4 0101_1100b saden_ur4 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b
F81865 may, 2010 v0.28p 115 9bit-mode slave address mask register ? index f5h bit name r/w default description 7:0 saden_ur4 r/w 00h this byte accompanying with saddr_ur4 will determine the given address and broadcast address in 9-bit mode. the uart_ur4 will response to both given and broadcast address. follow the description to determine the given address and broadcast address: 15. given address: if bit n of saden_ur4 is ?0?, then the corresponding bit of saddr_ur4 is don?t care. 16. broadcast address: if bit n of ored saddr_ur4 and saden_ur4 is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr_ur4 0101_1100b saden_ur4 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b 8.15 uart5 registers (cr14) uart 5 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 ur5_en r/w 0 0: disable uart 5. 1: enable uart 5. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of uart 5 base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 00h the lsb of uart 5 base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selur5irq r/w 3h select t he irq channel for uart 5. irq share register ? index f0h bit name r/w default description 7 ur5_9bit_mode r/w 0 0: normal uart function 1: enable 9-bit mode (multi-drop mode). in the 9-bit mode, the parity bit becomes the address/data bit. 6 ur5_auto_addr r/w 0 this bit works only in 9-bit mode. 0: the sm2 bit will be cleared by host, so that data could be received. 1: the sm2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by saddr_ur5 and saden_ur5) 5 ur5_rs485_inv r/w 0 invert rts# if ur5_rs485_en is set. 4 ur5_rs485_en r/w 0 0: rs232 driver. 1: rs485 driver. auto drive rts# high when transmitting data, otherwise is kept low .
F81865 may, 2010 v0.28p 116 3-2 reserved - - reserved. 1 ur5irq_mode r/w 0 0 : pci irq sharing mode. 1 : isa irq sharing mode. this bit is effective in irq sharing mode. 0 ur5irq_share r/w 0 0 : irq is not sharing with other device. 1 : irq is sharing with other device. clock register ? index f2h bit name r/w default description 7-2 reserved - - reserved. 1-0 ur5_clk_sel r/w 00b select the clock source for uart5. 00: 1.8432mhz. 01: 18.432mhz. 10: 24mhz. 11: 14.769mhz. 9bit-mode slave address register ? index f4h bit name r/w default description 7-0 saddr_ur5 r/w 00h this byte accompanying with saden_ur5 will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. follow the description to determine the given address and broadcast address: 17. given address: if bit n of saden_ur5 is ?0?, then the corresponding bit of saddr_ur5 is don?t care. 18. broadcast address: if bit n of ored saddr_ur5 and saden_ur5 is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr_ur5 0101_1100b saden_ur5 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b 9bit-mode slave address mask register ? index f5h bit name r/w default description 7:0 saden_ur5 r/w 00h this byte accompanying with saddr_ur5 will determine the given address and broadcast address in 9-bit mode. the uart_ur5 will response to both given and broadcast address. follow the description to determine the given address and broadcast address: 19. given address: if bit n of saden_ur5 is ?0?, then the corresponding bit of saddr_ur5 is don?t care. 20. broadcast address: if bit n of ored saddr_ur5 and saden_ur5 is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr_ur5 0101_1100b saden_ur5 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b
F81865 may, 2010 v0.28p 117 8.16 uart6 registers (cr15) uart 6 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 ur6_en r/w 0 0: disable uart 6. 1: enable uart 6. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of uart 6 base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 00h the lsb of uart 6 base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selur6irq r/w 3h select t he irq channel for uart 6. irq share register ? index f0h bit name r/w default description 7 ur6_9bit_mode r/w 0 0: normal uart function 1: enable 9-bit mode (multi-drop mode). in the 9-bit mode, the parity bit becomes the address/data bit. 6 ur6_auto_addr r/w 0 this bit works only in 9-bit mode. 0: the sm2 bit will be cleared by host, so that data could be received. 1: the sm2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by saddr_ur6 and saden_ur6) 5 ur6_rs485_inv r/w 0 invert rts# if ur6_rs485_en is set. 4 ur6_rs485_en r/w 0 0: rs232 driver. 1: rs485 driver. auto drive rts# high when transmitting data, otherwise is kept low . 3 rxw4c_ir r/w 0 0 : no reception delay when sir is changed from tx to rx. 1 : reception delay 4 character-time when sir is changed from tx to rx. 2 txw4c_ir r/w 0 0 : no transmission delay when sir is changed from rx to tx. 1 : transmission delay 4 character-time when sir is changed from rx to tx. 1 ur6irq_mode r/w 0 0 : pci irq sharing mode. 1 : isa irq sharing mode. this bit is effective in irq sharing mode. 0 ur6irq_share r/w 0 0 : irq is not sharing with other device. 1 : irq is sharing with other device. ir mode select register ? index f1h bit name r/w default description 7-5 reserved - - reserved. return 010b when read. 4-3 irmode1 irmode0 r/w 00b 0x: disable ir1 function. 10 : enable ir1 function, active pulse is 1.6us. 11 : enable ir1 function, active pulse is 3/16 bit time.
F81865 may, 2010 v0.28p 118 2 hduplx r/w 0 0 : full duplex function for ir self test. 1 : half duplex function. return 1 when read. 1 txinv_ir r/w 0 0 : irtx is not inversed. 1 : inverse the irtx. 0 rxinv_ir r/w 0 0 : irrx is not inversed. 1 : inverse the irrx. clock register ? index f2h bit name r/w default description 7-2 reserved - - reserved. 1-0 ur6_clk_sel r/w 00b select the clock source for uart6. 00: 1.8432mhz. 01: 18.432mhz. 10: 24mhz. 11: 14.769mhz. 9bit-mode slave address register ? index f4h bit name r/w default description 7-0 saddr_ur6 r/w 00h this byte accompanying with saden_ur6 will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. follow the description to determine the given address and broadcast address: 21. given address: if bit n of saden_ur6 is ?0?, then the corresponding bit of saddr_ur6 is don?t care. 22. broadcast address: if bit n of ored saddr_ur6 and saden_ur6 is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr_ur6 0101_1100b saden_ur6 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b 9bit-mode slave address mask register ? index f5h bit name r/w default description 7:0 saden_ur6 r/w 00h this byte accompanying with saddr_ur6 will determine the given address and broadcast address in 9-bit mode. the uart_ur6 will response to both given and broadcast address. follow the description to determine the given address and broadcast address: 23. given address: if bit n of saden_ur6 is ?0?, then the corresponding bit of saddr_ur6 is don?t care. 24. broadcast address: if bit n of ored saddr_ur6 and saden_ur6 is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr_ur6 0101_1100b saden_ur6 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b
F81865 may, 2010 v0.28p 119 9. electrical characteristics 9.1 absolute maximum ratings parameter rating unit power supply voltage -0.5 to 5.5 v input voltage -0.5 to vdd+0.5 v operating temperature 0 to +70 c operating temperature-i -40 to +85 c storage temperature -55 to 150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device 9.2 dc characteristics (t a = 0 c to 70 c, vdd = 3.3v 10%, vss = 0v ) parameter conditions min typ max unit temperature error, remote diode 60 o c < t d < 145 o c, vcc = 3.0v to 3.6v 0 o c F81865 may, 2010 v0.28p 120 output low current iol +12 ma vol = 0.4v o 8 -output pin with 8 ma sink/source capability. output high current iol -8 ma voh = 2.4v output low current iol +8 ma vol = 0.4v od 14 -open drain output pin with 14 ma sink capability. output low current iol +14 ma vol = 0.4v od 16,u10,5v -open drain output pin with 14 ma sink capabilit y, internal 10k ohms pull-up and 5v tolerance. output low current iol +16 ma vol = 0.4v od 24 -open drain output pin with 24 ma sink capability, 5v tolerance. output low current iol +24 ma vol = 0.4v i/o 12st,5v -ttl level bi-directional pin with schmitt trigger, open-drain output with12 ma sink capability, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v output high current iol -12 ma voh = 2.4v output low current iol +12 ma vol = 0.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v i/o 8t -ttl level bi-directional pin with schmitt trigge r, open-drain output with 8ma sink capability. input low voltage vil 0.8 v input high voltage vih 2.0 v output high current iol -8 ma voh = 2.4v output low current iol +8 ma vol = 0.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v i/ood 12t -ttl level bi-directional pin with schmitt trigge r, output with 12 ma sink/source capability or open drain with 12ma sink capability, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v output high current iol -12 ma voh = 0.4v output low current iol +12 ma vol = 0.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v i/ood 14 -ttl level bi-directional pin with schmitt trigge r, output with 14 ma sink/source capability or open drain with 14ma sink capability, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v output high current iol -14 ma voh = 0.4v output low current iol +14 ma vol = 0.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v i/ood 8 -ttl level bi-directional pin with schmitt trigge r, output with 8 ma sink/source capability or open drain with 8ma sink capability, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v output high current iol -8 ma voh = 0.4v output low current iol +8 ma vol = 0.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v i/od 16t,5v -ttl level bi-directional pin, open-drain ou tput with16 ma sink capability, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v output low current iol +16 ma vol = 0.4v input high leakage ilih +1 a vin = vdd
F81865 may, 2010 v0.28p 121 input low leakage ilil -1 a vin = 0v i/o 24t -ttl level bi-directional pin, output pin with 24ma sink/source capability. input low threshold voltage vt- 0.8 v vdd = 3.3 v input high threshold voltage vt+ 2.0 v vdd = 3.3 v output low current iol -24 ma vol = 0.4 v output high current ioh +24 ma voh = 2.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v
F81865 may, 2010 v0.28p 122 10. ordering information part number package type production flow F81865f-i 128-pqfp green package industrial, -40 c to +85 c F81865f 128-pqfp green package commercial, 0 c to +70 c
F81865 may, 2010 v0.28p 123 11. package dimensions 128 pqfp feature integration technology inc. headquarters taipei office 3f-7, no 36, tai yuan st., bldg. k4, 7f, no.700, chung cheng rd., chupei city, hsinchu, taiwan 302, r.o.c. chungho city, taipei, taiwan 235, r.o.c. tel : 886-3-5600168 tel : 866-2-8227-8027 fax : 886-3-5600166 fax : 866-2-8227-8037 www: http://www.fintek.com.tw please note that all datasheet and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this datasheet belong to their respective owne r
F81865 may, 2010 v0.28p 124 12. application circuit tit le size document number rev date: sheet of 0.1 F81865f-chip b 11 thursday , december 18, 2008 ps_on# wdata#/gpio53/dcd6# led_vcc ri4# slin# ri1# slct fanctl2 led_vsb spi_mosi s3# dir#/gpio54/ri6# init# ack# busy pe slin# err# init# afd# stb# pd0 cts1# pd1 copen# pd2 pd3 pd4 pd5 pd6 cts4# pd7 dcd1# pwsout# ri1# cts1# dtr1# copen# step#/gpio55/cts6# rts1# dsr1# sout1 sin1 err# kclk dcd2# 1 ri2# 2 cts2 3 dtr2# 4 rts2# 5 dsr2# 6 sout2 7 sin2 8 densel#/gpio50/rts6_2# 9 moa#/ gpi o51/si n6_2/ irrx2 10 drva#/gpio52/ sout6_2/i rtx2 11 wdata#/gpi o53/ dcd6# 12 dir#/gpio54/ri6# 13 step#/gpio55/ cts6# 14 hdsel#/ gpio56/dtr6# 15 wgate#/gpi o57/ dsr6# 16 rdata#/gpio60/dcd5# 17 trk0#/gpio61/ri5# 18 index#/ gpio62/cts5# 19 wpt#/ gpi o63/dtr5# 20 dskchg#/gpio64/dsr5# 21 gnd 22 lreset# 23 ldrq# 24 serirq 25 lfram# 26 lad0 27 lad1 28 lad2 29 lad3 30 vcc 31 pciclk 32 clkin 33 kbrst# 34 ga20 35 dcd3#/gpio30 36 ri 3#/ gpi o31 37 cts3#/gpio32 38 kclk 64 kdata 63 mc lk 62 mdata 61 vsb 60 gpio07/rts6_1# 59 gpio06/sin6_1/irrx1 58 gpio05/sout6_1/irtx1 57 gpio04/fwh_dis/spi_csi# 56 gpio03/spi_mosi 55 gpio02/spi_miso 54 gpio01/spi_cs0# 53 gpio00/spi_clk 52 sin4/gpio47 51 sout4/gpio46 50 dsr4#/gpio45 49 rts4#/gpio44 48 dtr4#/gpio43 47 cts4#/gpio42 46 ri4#/gpio41 45 dcd4#/gpio40 44 sin3#/gpio37 43 sout3/gpio36 42 dsr3#/gpio35 41 rts3#/gpio34 40 dtr3#/gpio33 39 slct 102 fanctl2 101 fanin2 100 fanctl1 99 fanin1 98 vcc 97 vin0(vcore) 96 vi n1 95 vi n2 94 vi n3 93 vref 92 d1+(cpu) 91 d2+ 90 agnd(d-) 89 rtc_vbat 88 rtx_x2 87 rtc_x1 86 copen# 85 vbat 84 rsmrst#/ gpio27 83 pwok/ gpi o26 82 ps_on#/ gpio25 81 s3#/ gpio24 80 pwsout#/ gpio23 79 pwsin#/ gpio22 78 atx pg_i n/ gpio21 77 alert#/ gpio20 76 ovt# 75 pme# 74 gnd 73 peci/gpio17 72 beep/ gpio16 71 wdtrst#/ gpio15 70 gpio14/rts5# 69 gpio13/sda/sin5 68 gpio12/scl/sout5 67 gpi o11/ led_vcc 66 gpio10/ led_vsb 65 pe 103 busy 104 ack# 105 slin# 106 init# 107 err# 108 afd# 109 stb# 110 pd0 111 pd1 112 pd2 113 pd3 114 pd4 115 pd5 116 pd6 117 pd7 118 vcc 119 dcd1# 120 ri1# 121 cts1# 122 dtr1# 123 rts1# 124 dsr1# 125 sout1 126 sin1 127 gnd 128 F81865f u1 F81865 irtx1 kdata mc lk dtr1# md ata vcc_119 gpio07/rts6_1# irrx1 pwsin# irtx1 fwh_dis d2+ spi_mosi hdsel#/gpio56/dtr6# spi_miso spi_cs0# spi_clk dtr4# afd# sin4 sout4 rts1# dsr4# rts4# dtr4# alert# cts4# irrx1 d1+(cpu) ri4# agnd(d-) wgate#/gpio57/dsr6# dcd4# sin3 stb# sout3 dsr3# r7 10m rtc_vbat c6 0.1u dsr1# rts3# dtr3# peci wpt#/gpio63/dtr5# pcirst# dskchg#/gpio64/dsr5# ldrq# wpt#/gpio63/dtr5# serirq dskchg#/gpio64/dsr5# serirq ldrq# pcirst# rsmrst# lfram# rts4# lfram# index#/gpio62/cts5# vref rdata#/gpio60/dcd5# trk0#/gpio61/ri5# pd0 vsb_60 dtr1# r8 1k r8 on: fan100% off: fan60% r9 on: spi as a primary bios off: spi as a back up bios r10 on: i2c 5a off:i2c 5c r11 on: dac off:pwm r12 on: config 2e off :config 4e r13 on: spi_enable off: spi_disable sout2 r10 1k r11 1k rdata#/gpio60/dcd5# r12 1k r9 1k md ata sout1 dtr2# rts1# rts2# sout1 power trip r r13 1k wgate#/gpio57/dsr6# d2+ dtr3# beep r1 0 vin3 hdsel#/gpio56/dtr6# trk0#/gpio61/ri5# pwok pd1 step#/gpio55/cts6# lad1 pciclk lad3 lad3 lad2 pciclk lad0 lad0 lad1 lad2 d1+(cpu) dsr4# sin1 dir#/gpio54/ri6# ps_on# wdtrst# vcc3v wdata#/gpio53/dcd6# vin2 ovt# mc lk index#/gpio62/cts5# vref s3# drva#/gpio52 pd2 r2 1k r3 1k r6 1k r5 1k rts3# r4 1k vcc5v wpt#/gpio63/dtr5# trk0#/gpio61/ri5# index#/gpio62/cts5# vsb3v rdata#/gpio60/dcd5# dskchg#/gpio64/dsr5# dcd2# moa#/gpio51 gpio14/rts5# pwsout# densel#/gpio50 ri3# cts3# ri3# cts3# vin1 pme# sout4 vbat sin2 pwsin# vin3 ri2# sout2 kdata sin5 vcc3v dsr2# atxpg_in vin0(vcore) dsr3# pwok vin2 rts2# clk24/48m clk24/48m ga20 kbrst# ga20 kbrst# alert# cts2# y1 crystal vcc3v dtr2# c7 0.1u kclk sin4 sout5 pd3 vin1 cts2# slct rtc_x1 ovt# rtc_x1 rsmrst# ri2# dtr2# sout3 pme# vin0(vcore) led_vcc dcd2# dcd3# pd4 rtx_x2 atxpg_in r tx_x2 spi_clk gpio07/rts6_1# dcd3# rts2# peci led_vsb pd5 densel#/gpio50 index#/gpio62/cts5# moa#/ gpi o51 drva#/gpio52 rtc_vbat step#/gpio55/cts6# dir#/gpio54/ri6# rdata#/gpio60/dcd5# wgate#/gpio57/dsr6# trk0#/gpio61/ri5# wpt#/gpio63/dtr5# wdata#/gpio53/dcd6# hdsel#/gpio56/dtr6# dskchg#/gpio64/dsr5# c2 0.1u beep 2 2 4 4 6 6 8 8 10 10 12 12 14 14 16 16 18 18 20 20 22 22 24 24 26 26 28 28 30 30 32 32 34 34 1 1 3 3 5 5 7 7 9 9 11 11 13 13 15 15 17 17 19 19 21 21 23 23 25 25 27 27 29 29 31 31 33 33 j1 header 17x2 floppy conn. sin3 densel#/gpio50 fwh_dis dsr2# pe c3 10p wdtrst# c5 0.1u pd6 spi_miso fanctl1 fanin1 c4 10p moa#/gpio51 gpio14/rts5# fanin1 sout2 c1 0.1u busy dcd4# pd7 fanctl1 sin5 drva#/gpio52 fanin2 spi_cs0# sin2 ack# sout5 dcd1# fanin2 fanctl2
F81865 may, 2010 v0.28p 125 tit le size document number rev date: sheet of 0.1 com_printer_ps2 custom 11 thursday , december 18, 2008 md at vcc5v r62 4.7k r63 4.7k c44 100p c45 0.1u l2 fb l4 fb c43 100p ps2 mouse interface 1 2 3 4 5 6 js1 m-din_6-r l3 fb r64 4.7k c46 100p 1 2 3 4 5 6 js2 m-din_6-r c48 0.1u l5 fb c47 100p r65 4.7k ps2 keyboard interface 1 2 3 j26 con3 kdat mc lk kclk vsb5v cts4# ri4# rts4# dsr4# sin4 dtr4# dcd4# sout4 cts1# ri1# rts1# dsr1# ra1 2 ra2 3 ra3 4 dy1 5 dy2 6 ra4 7 dy3 8 ra9 9 +12v 1 -12v 10 gnd 11 vcc 20 ry1 19 ry2 18 ry3 17 da1 16 da2 15 ry4 14 da3 13 ry5 12 u13 uart ra1 2 ra2 3 ra3 4 dy1 5 dy2 6 ra4 7 dy3 8 ra9 9 +12v 1 -12v 10 gnd 11 vcc 20 ry1 19 ry2 18 ry3 17 da1 16 da2 15 ry4 14 da3 13 ry5 12 u14 uart ra1 2 ra2 3 ra3 4 dy1 5 dy2 6 ra4 7 dy3 8 ra9 9 +12v 1 -12v 10 gnd 11 vcc 20 ry1 19 ry2 18 ry3 17 da1 16 da2 15 ry4 14 da3 13 ry5 12 u15 uart sin1 dtr1# dcd1# sout1 ra1 2 ra2 3 ra3 4 dy1 5 dy2 6 ra4 7 dy3 8 ra9 9 +12v 1 -12v 10 gnd 11 vcc 20 ry1 19 ry2 18 ry3 17 da1 16 da2 15 ry4 14 da3 13 ry5 12 u12 uart +12v -12v uart 1 port interface vcc5v dtrn2 rin2 dsrn2 rtsn2 sinn2 ctsn2 soutn2 gnd soutn2 ctsn2 dsrn2 dcdn2 dcdn2 sinn2 dtrn2 rtsn2 5 9 4 8 3 7 2 6 1 p2 uart db9 rin2 uart 2 port interface dtrn1 gnd dsrn1 ctsn1 sinn1 rtsn1 dcdn1 soutn1 ctsn1 dtrn1 dsrn1 sinn1 rin1 dcdn1 5 9 4 8 3 7 2 6 1 p1 uart db9 rtsn1 soutn1 -12v +12v trk0#/gpio61/ri5# vcc5v dskchg#/gpio64/dsr5# index#/gpio62/cts5# wpt#/gpio63/dtr5# gpio14/rts5# sout5 sin5 rdata#/gpio60/dcd5# +12v ra1 2 ra2 3 ra3 4 dy1 5 dy2 6 ra4 7 dy3 8 ra9 9 +12v 1 -12v 10 gnd 11 vcc 20 ry1 19 ry2 18 ry3 17 da1 16 da2 15 ry4 14 da3 13 ry5 12 u16 uart -12v vcc5v rin5 dtrn5 ctsn5 dsrn5 rtsn5 sinn5 ctsn5 soutn5 gnd dcdn5 soutn5 sinn5 dsrn5 dcdn5 parallel port interface rin5 dtrn5 rtsn5 for lekage to power 5 9 4 8 3 7 2 6 1 p5 uart db9 1 2 3 4 5 6 7 8 rn9 33-8p4r 1 2 3 4 5 6 7 8 rn10 33-8p4r uart 5 port interface -12v +12v 1 2 3 4 5 6 7 8 rn5 2.7k-8p4r vcc5v rin3 dtrn3 ctsn3 dsrn3 rtsn3 sinn3 1 2 3 4 5 6 7 8 rn7 2.7k-8p4r ctsn3 soutn3 gnd dcdn3 soutn3 dsrn3 dcdn3 sinn3 dtrn3 rtsn3 5 9 4 8 3 7 2 6 1 p3 uart db9 rin3 uart 3 port interface cts2# ri2# rts2# dsr2# sin2 dtr2# dcd2# sout2 step#/gpio55/cts6# dir#/gpio54/ri6# gpio07/rts6_1# wgate#/gpio57/dsr6# sin6_1 hdsel#/gpio56/dtr6# wdata#/gpio53/dcd6# sout6_1 +12v ra1 2 ra2 3 ra3 4 dy1 5 dy2 6 ra4 7 dy3 8 ra9 9 +12v 1 -12v 10 gnd 11 vcc 20 ry1 19 ry2 18 ry3 17 da1 16 da2 15 ry4 14 da3 13 ry5 12 u17 uart -12v rin6 vcc5v dtrn6 dsrn6 rtsn6 ctsn6 +12v gnd sinn6 soutn6 soutn6 ctsn6 -12v dcdn6 sinn6 dsrn6 dcdn6 vcc5v rin4 1 2 3 4 5 6 7 8 rp1 rp4r_0 dtrn4 rtsn6 rtsn4 rin6 dtrn6 ctsn4 dsrn4 5 9 4 8 3 7 2 6 1 p6 uart db9 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 j16 db25 uart 6 port interface gnd sinn4 ctsn4 soutn4 dcdn4 dcdn4 soutn4 1 2 3 4 5 6 7 8 rn6 2.7k-8p4r sinn4 dsrn4 rtsn4 rin4 dtrn4 1 2 3 4 5 6 7 8 rn4 2.7k-8p4r 5 9 4 8 3 7 2 6 1 p4 uart db9 uart 4 port interface ri3# dsr3# cts3# dtr3# rts3# sout3 sin3 dcd3# r61 2.7k (female) vcc5v 1 2 d14 1n5819 c40 180p c26 180p c34 180p c27 180p c35 180p c28 180p c36 180p c29 180p c37 180p c30 180p c38 180p c31 180p c39 180p c32 180p c41 180p c33 180p c42 180p init# slin# afd# err# pd0 stb# pd2 pd1 slct pd3 pd5 pd4 pd6 pe pd7 busy ack#
F81865 may, 2010 v0.28p 126 r25 1k copen# r21 2m vbat c31 1000p tit le size document number rev date: sheet of 0.1 fan b 34 wednesday , march 05, 2008 1 2 sw1 r20 100 case open circuit 1 2 c34 0.1u 2 1 j4 li-bat socket d3 diode copen# rtc_vbat fanin1 fanctl2 1 2 3 4 jp1 4 header fanin_1 vcc5v r19 10k r22 4.7k r24 10k r23 27k +12v d2 1n4148 + c33 47u c32 0.1u fan1 control circuit pwm fanctl1 fanin2 c36 0.1u r31 10k r30 27k 2 1 3 q1 pnp r27 4.7k r26 4.7k r28 4.7k +12v + c35 47u 1 2 3 jp2 header 3 r29 330 g d s q2 mosfet n 2n7002 d4 1n4148 fan2 pwm control circuit
F81865 may, 2010 v0.28p 127 vin3 vref r66 10k 1% d1+ t rt1 thermistor 10k 1% (for system) spi_cs0# spi_miso q4 pnp 3906 for system r77 4.7k tit le size document number rev date: sheet of 0.1 b 44 friday , october 23, 2009 vcc3v from cpu d1+ vref d2+ r67 10k 1% t rt2 thermistor 10k 1% (for system) r36 200k r37 20k r38 100k r39 100k r34 47k r32 10k r33 200k thermistor sensing circuit agnd(d-) d2+ d- d1+ c39 3300p d+ c38 3300p d2+ q3 mosfet n chipset_reset c37 1uf bios reset circuit r35 100k temperature sensing diode sensing circuit agnd(d-) fwh_dis vcc5v +12v the best voltage input level is about 1v. voltage sensing. vram vcore spi_clk vin0(vcore) spi_mosi vin1 vin2 vcc3v r41 4.7k vcc3v hold# r40 4.7k w# q 2 s# 1 w# 3 vss 4 vcc 8 c 6 hold# 7 d 5 u6 spi flash memory vcc3v r42 4.7k <br> <a href='http://www.datasheet.hk/search.php?part=f81865&stype=part'>F81865</a> may, 2010 v0.28p 128 pci vcc5v -12v pwsout# s3# rsmrst# r83 4.7k vsb5v vsb3v +12v tit le size document number rev date: sheet of acpi sample <rev code> feature integration technology inc. b 17 thursday , october 30, 2008 south bridge north bridge cpu ata133 ide sata vsb5v pwsin# <a href='http://www.datasheet.hk/search.php?part=f81865&stype=part'>F81865</a> r84 4.7k 3v3 1 3v3 2 gnd 3 5v 4 gnd 5 5v 6 gnd 7 pw-ok 8 5vsb 9 3v3 11 -12v 12 gnd 13 ps-on 14 gnd 15 gnd 16 gnd 17 -5v 18 5v 19 12v 10 5v 20 atx1 atx connect atxpg_in r85 4.7k r86 4.7k pson# c59 22uf c60 cap np r105 pwr_btn lreset# r106 4.7k vsb5v vcc3v vsb3v psw+ 6 psw- 8 reset 7 rstgnd 5 u10 front panel vcc5v pclk_1,2,3(33mhz) <br></td> </tr> </table> <table border="0" width="980" id="table32" style="font-size:1px" height="10"> <tr> <td></td> </tr> </table> <table border="0" width="980" id="table31" style="font-size:1px" height="40"> <tr> <td background="images/bg03.gif"> <p align="right"><br> <font color="#FF0000"><a href="#top">▲Up To Search▲</a> </font></td> </tr> </table> <table border="0" width="980" id="table27"> <tr> <td> </td> </tr> <tr> <td> <b><font size="5">Price & Availability of F81865 </font></b> <a target="_blank" href="https://www.findchips.com/search/F81865"><img border="0" src="images/fc_logo.jpg" width="265" height="25"></a></td> </tr> <tr> <td><script src="http://www.findchips.com/api/inventory/search/F81865?limit=5&partner=18"></script> <script>document.getElementById("poweredBy").style.visibility="hidden";</script></td> </tr> </table> </div> <div align="center"> <table border="0" width="980" id="table13" style="font-size:12px"> <tr> <td> <table border="0" width="980" id="table26" style="font-size:1px"> <tr> <td background="images/bg03.gif"></td> </tr> </table> </td> </tr> <tr> <td> <p align="right">All Rights Reserved © <span lang="zh-cn"> IC-ON-LINE 2003 - 2022</span> </td> </tr> </table> </div> <div align="center"> <table border="0" width="980" id="table13" style="font-size:12px"> <tr> <td>[<a href="javascript:addbookmark()">Add Bookmark</a>] [<a href="mailto:ioldatasheet@gmail.com" target="_blank">Contact Us</a>] [<a href="link.php">Link exchange</a>] [<a href="privacy.php">Privacy policy</a>]</td> </tr> <tr> <td> Mirror Sites : [<a href="http://www.datasheet.hk">www.datasheet.hk</a>] [<a href="http://www.maxim4u.com">www.maxim4u.com</a>] [<a href="http://www.ic-on-line.cn">www.ic-on-line.cn</a>] [<a href="http://www.ic-on-line.com">www.ic-on-line.com</a>] [<a href="http://www.ic-on-line.net">www.ic-on-line.net</a>] [<a href="http://www.alldatasheet.com.cn">www.alldatasheet.com.cn</a>] [<a href="http://www.gdcy.com">www.gdcy.com</a>] [<a href="http://www.gdcy.net">www.gdcy.net</a>]<br><br><br></td> </tr> </table> </div> <style type="text/css"> .style1 { background-color: #333333; } .style2 { color: #FFFFFF; } .style3 { color: #0000FF; } .style4 { color: #FFFFFF; font-size: large; } .style5 { text-decoration: none; } .style6 { color: #6EF3F2; } .style7 { border-width: 0px; } </style> <a href="http://www.maxim4u.com/che_s1.php" rel="nofollow">.</a> <a href="http://www.maxim4u.com/che_s2.php" rel="nofollow">.</a> <a href="http://www.maxim4u.com/che_s3.php" rel="nofollow">.</a> <a href="http://www.maxim4u.com/che_s4.php" rel="nofollow">.</a> <a href="http://www.maxim4u.com/che_s5.php" rel="nofollow">.</a> <br> <div style="position:fixed ;bottom:0px;width:100%" id="id_cookies"> <table height="33" align="center" class="style1" style="width: 100%"> <tr> <td align="left" class="style2" style="width: 23px"> </td> <td align="left" class="style2">We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our <a href="privacy.php"> <span class="style6">Privacy Policy</span></a>.</td> <td align="center" class="style3" style="width: 100px"> <a href="javascript:iscookies()" class="style5"><span class="style4">X</span></a></td> </tr> </table></div> <script type="text/javascript" src="js/jquery.min.js"></script> <script type="text/javascript" src="js/cookie.js"></script> <script type="text/javascript"> $(function (){ if($.cookie("OkCookies") == 'OK') { document.getElementById('id_cookies').style.display="none"; } }); function iscookies(){ document.getElementById('id_cookies').style.display="none"; $.cookie("OkCookies",'OK',{ expires:3}); } </script> <script> (function(){ var bp = document.createElement('script'); var curProtocol = window.location.protocol.split(':')[0]; if (curProtocol === 'https') { bp.src = 'https://zz.bdstatic.com/linksubmit/push.js'; } else { bp.src = 'http://push.zhanzhang.baidu.com/push.js'; } var s = document.getElementsByTagName("script")[0]; s.parentNode.insertBefore(bp, s); })(); </script> <script type="text/javascript"> var _gaq = _gaq || []; _gaq.push(['_setAccount', 'UA-280427-2']); _gaq.push(['_trackPageview']); (function() { var ga = document.createElement('script'); ga.type = 'text/javascript'; ga.async = true; ga.src = ('https:' == document.location.protocol ? 'https://ssl' : 'http://www') + '.google-analytics.com/ga.js'; var s = document.getElementsByTagName('script')[0]; s.parentNode.insertBefore(ga, s); })(); </script> <script src="http://www.google-analytics.com/urchin.js" type="text/javascript"> </script> <script type="text/javascript"> _uacct = "UA-280427-1"; urchinTracker(); </script> <script> var _hmt = _hmt || []; (function() { var hm = document.createElement("script"); hm.src = "//hm.baidu.com/hm.js?db7b417c2a40fa0c35a5e98cab960d1b"; var s = document.getElementsByTagName("script")[0]; s.parentNode.insertBefore(hm, s); })(); </script> </body> </html>

	To Download F81865 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .